A method for correcting the functionality of a wire-pipelined circuit. - Vidyasagar Nookala; Sachin S. Sapatnekar (DAC, 2004)

Microarchitecture-aware floorplanning using a statistical design of experiments approach. - Vidyasagar Nookala; Ying Chen; David J. Lilja; Sachin S. Sapatnekar (DAC, 2005)

Robust gate sizing by geometric programming. - Jaskirat Singh; Vidyasagar Nookala; Zhi-Quan Luo; Sachin S. Sapatnekar (DAC, 2005)

Designing optimized pipelined global interconnects: algorithms and methodology impact. - Vidyasagar Nookala; Sachin S. Sapatnekar (ISCAS (1), 2005)

Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. - Vidyasagar Nookala; David J. Lilja; Sachin S. Sapatnekar (ISLPED, 2006)

Comparing simulation techniques for microarchitecture-aware floorplanning. - Vidyasagar Nookala; Ying Chen; David J. Lilja; Sachin S. Sapatnekar (ISPASS, 2006)