RTL bug localization through LTL specification mining (WIP). - Vighnesh Iyer; Donggyu Kim; Borivoje Nikolic; Sanjit A. Seshia (MEMOCODE, 2019)

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures. - Hasan Genc; Ameer Haj-Ali; Vighnesh Iyer; Alon Amid; Howard Mao; John Charles Wright; Colin Schmidt 001; Jerry Zhao; Albert J. Ou; Max Banister; Yakun Sophia Shao; Borivoje Nikolic; et al. (CoRR, 2019)

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. - John Charles Wright; Colin Schmidt 001; Ben Keller; Daniel Palmer Dabbelt; Jaehwa Kwak; Vighnesh Iyer; Nandish Mehta; Pi-Feng Chiu; Stevo Bailey; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. - Hasan Genc; Seah Kim; Alon Amid; Ameer Haj-Ali; Vighnesh Iyer; Pranav Prakash; Jerry Zhao; Daniel Grubb; Harrison Liew; Howard Mao; Albert J. Ou; Colin Schmidt 001; et al. (DAC, 2021)

Pattern Census: A Characterization of Pattern Usage in Early Programming Courses. - Vighnesh Iyer; Craig B. Zilles (SIGCSE, 2021)

A Review of Emotion Detection Systems. - Aditi Deo; Dhrumil Thakore; Riddhi Mistry; Vighnesh Iyer; Prachi Tawde (IC3I, 2022)

Simulator Independent Coverage for RTL Hardware Languages. - Kevin Laeufer; Vighnesh Iyer; David Biancolin; Jonathan Bachrach; Borivoje Nikolic; Koushik Sen (ASPLOS (3), 2023)

RTL-Repair: Fast Symbolic Repair of Hardware Design Code. - Kevin Laeufer; Brandon Fajardo; Abhik Ahuja; Vighnesh Iyer; Borivoje Nikolic; Koushik Sen (ASPLOS (3), 2024)