Heuristic Minimization of Synchronous Relations. - Vigyan Singhal; Yosinori Watanabe; Robert K. Brayton (ICCD, 1993)

Formula-Dependent Equivalence for Compositional CTL Model Checking. - Adnan Aziz; Thomas R. Shiple; Vigyan Singhal (CAV, 1994)

The Verifiacation Problem for Safe Replaceability. - Vigyan Singhal; Carl Pixley (CAV, 1994)

HSIS: A BDD-Based Environment for Formal Verification. - Adnan Aziz; Felice Balarin; Szu-Tsung Cheng; Ramin Hojati; Timothy Kam; Sriram C. Krishnan; Rajeev K. Ranjan 001; Thomas R. Shiple; Vigyan Singhal; Serdar Tasiran; Huey-Yih Wang; Robert K. Brayton; et al. (DAC, 1994)

Multi-level synthesis for safe replaceability. - Carl Pixley; Vigyan Singhal; Adnan Aziz; Robert K. Brayton (ICCAD, 1994)

Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. - Adnan Aziz; Vigyan Singhal; Gitanjali Swamy; Robert K. Brayton (ICCD, 1994)

It Usually Works: The Temporal Logic of Stochastic Systems. - Adnan Aziz; Vigyan Singhal; Felice Balarin (CAV, 1995)

The Validity of Retiming Sequential Circuits. - Vigyan Singhal; Carl Pixley; Richard L. Rudell; Robert K. Brayton (DAC, 1995)

Exploiting power-up delay for sequential optimization. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Robert K. Brayton (EURO-DAC, 1995)

Incremental methods for FSM traversal. - Gitanjali Swamy; Robert K. Brayton; Vigyan Singhal (ICCD, 1995)

Power-Up Delay for Retiming Digital Circuits. - Vigyan Singhal; Robert K. Brayton; Carl Pixley (ISCAS, 1995)

Verifying Continuous Time Markov Chains. - Adnan Aziz; Kumud Sanwal; Vigyan Singhal; Robert K. Brayton (CAV, 1996)

The case for retiming with explicit reset circuitry. - Vigyan Singhal; Sharad Malik; Robert K. Brayton (ICCAD, 1996)

Latch Redundancy Removal Without Global Reset. - Shaz Qadeer; Robert K. Brayton; Vigyan Singhal (ICCD, 1996)

Optimizing Designs Containing Black Boxes. - Tai-Hung Liu; Khurram Sajid; Adnan Aziz; Vigyan Singhal (DAC, 1997)

Sequential optimisation without state space exploration. - Amit Mehrotra; Shaz Qadeer; Vigyan Singhal; Robert K. Brayton; Adnan Aziz; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

Analysis of Locking Behavior in Three Real Database Systems. - Vigyan Singhal; Alan Jay Smith (VLDB J., 1997)

Robust latch mapping for combinational equivalence checking. - Jerry R. Burch; Vigyan Singhal (ICCAD, 1998)

Tight integration of combinational verification methods. - Jerry R. Burch; Vigyan Singhal (ICCAD, 1998)

On the optimization power of retiming and resynthesis transformations. - Rajeev K. Ranjan 001; Vigyan Singhal; Fabio Somenzi; Robert K. Brayton (ICCAD, 1998)

Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. - Jason Baumgartner; Tamir Heyman; Vigyan Singhal; Adnan Aziz (CAV, 1999)

Using Combinational Verification for Sequential Circuits. - Rajeev K. Ranjan 001; Vigyan Singhal; Fabio Somenzi; Robert K. Brayton (DATE, 1999)

BDD Decomposition for Efficient Logic Synthesis. - Congguang Yang; Maciej J. Ciesielski; Vigyan Singhal (ICCD, 1999)

Equivalences for Fair Kripke Structures. - Adnan Aziz; Felice Balarin; Vigyan Singhal; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (Chic. J. Theor. Comput. Sci., 1999)

Model Checking: A Hardware Design Perspective. - Carl Pixley; Vigyan Singhal (Int. J. Softw. Tools Technol. Transf., 1999)

An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. - Jason Baumgartner; Anson Tripp; Adnan Aziz; Vigyan Singhal; Flemming Andersen (CAV, 2000)

BDS: a BDD-based logic optimization system. - Congguang Yang; Maciej J. Ciesielski; Vigyan Singhal (DAC, 2000)

Automatic Lighthouse Generation for Directed State Space Search. - Praveen Yalagandula; Adnan Aziz; Vigyan Singhal (DATE, 2000)

Model-checking continous-time Markov chains. - Adnan Aziz; Kumud Sanwal; Vigyan Singhal; Robert K. Brayton (ACM Trans. Comput. Log., 2000)

SIVA: A System for Coverage-Directed State Space Search. - Malay K. Ganai; Praveen Yalagandula; Adnan Aziz; Andreas Kuehlmann; Vigyan Singhal (J. Electron. Test., 2001)

Theory of safe replacements for sequential circuits. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Optimizing designs containing black boxes. - Tai-Hung Liu; Adnan Aziz; Vigyan Singhal (ACM Trans. Design Autom. Electr. Syst., 2001)

Formula-Dependent Equivalence for Compositional CTL Model Checking. - Adnan Aziz; Thomas R. Shiple; Vigyan Singhal; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (Formal Methods Syst. Des., 2002)

An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. - Jason Baumgartner; Tamir Heyman; Vigyan Singhal; Adnan Aziz (Formal Methods Syst. Des., 2003)

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. - Anuj Goel; Khurram Sajid; Hai Zhou 001; Adnan Aziz; Vigyan Singhal (Formal Methods Syst. Des., 2003)

Sequential optimization in the absence of global reset. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Shaz Qadeer; Robert K. Brayton (ACM Trans. Design Autom. Electr. Syst., 2003)

Formal Verification of a Public-Domain DDR2 Controller Design. - Abhishek Datta; Vigyan Singhal (VLSI Design, 2008)

Using Coverage to Deploy Formal Verification in a Simulation World. - Vigyan Singhal; Prashant Aggarwal (CAV, 2011)

Planning for end-to-end formal using simulation-based coverage: invited tutorial. - Prashant Aggarwal; Darrow Chu; Vijay Kadamby; Vigyan Singhal (FMCAD, 2011)

Liveness vs Safety - A Practical Viewpoint. - B. A. Krishna; Jonathan Michelson; Vigyan Singhal; Alok Jain (Haifa Verification Conference, 2011)

Compositional Reasoning Gotchas in Practice. - Chirag Agarwal; Paul Hylander; Yogesh Mahajan; Jonathan Michelson; Vigyan Singhal (FMCAD, 2015)