A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter. - Vijay Dhanasekaran; Manisha Gambhir; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2007)

Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band Gm-C Filters. - Manisha Gambhir; Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A low power 1.3GHz dual-path current mode Gm-C filter. - Manisha Gambhir; Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (CICC, 2008)

A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF. - Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (ISSCC, 2008)

A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element. - Vijay Dhanasekaran; Manisha Gambhir; Mohamed M. Elsayed; Edgar Sánchez-Sinencio; José Silva-Martínez; Chinmaya Mishra; Lei Chen; Erik Pankratz (ISSCC, 2009)

Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance. - Vijay Dhanasekaran; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2009)

A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element. - Vijay Dhanasekaran; Manisha Gambhir; Mohamed M. Elsayed; Edgar Sánchez-Sinencio; José Silva-Martínez; Chinmaya Mishra; Lei Chen; Erik Pankratz (IEEE J. Solid State Circuits, 2011)

A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. - Mohamed M. Elsayed; Vijay Dhanasekaran; Manisha Gambhir; José Silva-Martínez; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2011)