A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. - Vijay Khawshe; Pravin V. Kumar; Renu Rangnekar; Kapil Vyas; Kashi Prabu; Mahabaleshwara; Manish Jain; Navin K. Mishra; Abhijit Abhyankar (VLSI Design, 2007)

A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. - Vijay Khawshe; Kapil Vyas; Renu Rangnekar; Prateek Goyal; Vijay Krishna; Kashinath Prabhu; Pravin Kumar Venkatesan; Leneesh Raghavan; Rajkumar Palwai; M. Thrivikraman; Kunal Desai; Abhijit Abhyankar (VLSI Design, 2009)

High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. - Kunal Desai; Rajasekhar Nagulapalli; Vijay Krishna; Rajkumar Palwai; Pravin Kumar Venkatesan; Vijay Khawshe (VLSI Design, 2010)