A formal method for computer design verification. - Vijay Pitchumani; Edward P. Stabler (DAC, 1982)

Formal verification of a real-time hardware design. - Zerksis D. Umrigar; Vijay Pitchumani (DAC, 1983)

An Inductive Assertion Method for Register Transfer Level Design Verification. - Vijay Pitchumani; Edward P. Stabler (IEEE Trans. Computers, 1983)

An Experiment in Programming with Full First-Order Logic. - Zerksis D. Umrigar; Vijay Pitchumani (SLP, 1985)

Verification of Register Transfer Level Parallel Control Sequences. - Vijay Pitchumani; Edward P. Stabler (IEEE Trans. Computers, 1985)

A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing. - Vijay Pitchumani; Qisui Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

: A Parallel Algorithm for Fault Simulation on the Connection Machine. - Vinod Narayanan; Vijay Pitchumani (ITC, 1988)

Functional Test Generation Based on Unate Function Theory. - Vijay Pitchumani; Satish S. Soman (IEEE Trans. Computers, 1988)

Compaction of a Routed Channel on the Connection Machine. - Shantanu Ganguly; Vijay Pitchumani (DAC, 1989)

A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. - Vinod Narayanan; Vijay Pitchumani (DAC, 1989)

Restricted symbolic evaluation is fast and useful. - J. Lawrence Carter; Barry K. Rosen; Gordon L. Smith; Vijay Pitchumani (ICCAD, 1989)

A System for Fault Diagnosis and Simulation of VHDL Descriptions. - Vijay Pitchumani; Pankaj Mayor; Nimish Radia (DAC, 1991)

Fault Diagnosis using Functional Fault Models for VHDL descriptions. - Vijay Pitchumani; Pankaj Mayor; Nimish Radia (ITC, 1991)

A VHDL Fault Diagnosis Tool Using Functional Fault Models. - Vijay Pitchumani; Pankaj Mayor; Nimish Radia (IEEE Des. Test Comput., 1992)

Fault simulation on massively parallel SIMD machines algorithms, implementations and results. - Vinod Narayanan; Vijay Pitchumani (J. Electron. Test., 1992)

Solving the scheduling problem in high level synthesis using a normalized mean field neural network. - M. Kemal Unaltuna; Mehmet Emin Dalkiliç; Vijay Pitchumani (ICNN, 1993)

Quadrisectioning Based Placement with a Normalized Mean Field Neural Network. - M. Kemal Unaltuna; Vijay Pitchumani (ISCAS, 1993)

Optimal Operation Scheduling Using Resource Lower Bound Estimations. - Mehmet Emin Dalkiliç; Vijay Pitchumani (EDAC-ETC-EUROASIC, 1994)

Distributed data-path synthesis on a network of workstations. - Mehmet Emin Dalkiliç; Vijay Pitchumani (Great Lakes Symposium on VLSI, 1994)

A Multi-Schedule Approach to High-Level Synthesis. - Mehmet Emin Dalkiliç; Vijay Pitchumani (ICCD, 1994)

A Stochastic Reward & Punishment Neural Network Algorithm for Circuit Bipartitioning. - M. Kemal Unaltuna; Vijay Pitchumani (ISCAS, 1994)

HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. - Neeta Ganguly; Vijay Pitchumani (VLSI Design, 1994)

ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis. - M. Kemal Unaltuna; Vijay Pitchumani (ISCAS, 1995)

Multi-schedule design space exploration: an alternative synthesis framework. - Mehmet Emin Dalkiliç; Vijay Pitchumani (Integr., 1999)

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? - Chung-Kuan Cheng; Steve Lin; Andrew B. Kahng; Keh-Jeng Chang; Vijay Pitchumani; Toshiyuki Shibuya; Roberto Suaya; Zhiping Yu; Fook-Luen Heng; Don MacMillen (ASP-DAC, 2005)

Embedded tutorial I: design for manufacturability. - Vijay Pitchumani (ASP-DAC, 2005)

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannal Yang; Prashant Saxena; Vijay Pitchumani (ISCAS (6), 2005)

A Hitchhiker's Guide to the DFM Universe. - Vijay Pitchumani (APCCAS, 2006)

Variation-aware analysis: savior of the nanometer era? - Sani R. Nassif; Vijay Pitchumani; Norma Rodriguez; Dennis Sylvester; Clive Bittlestone; Riko Radojcic (DAC, 2006)

Integrating dynamic thermal via planning with 3D floorplanning algorithm. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Shan Zeng; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (ISPD, 2006)

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani (ACM Trans. Design Autom. Electr. Syst., 2006)

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Shan Zeng; Jinian Bian; Wenjian Yu; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Who solves the variability problem? - Nagaraj Ns; Juan C. Rey; Jamil Kawa; Robert C. Aitken; Christian Lütkemeyer; Vijay Pitchumani; Andrzej J. Strojwas; Steve Trimberger (DAC, 2010)

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. - Moongon Jung; Taigon Song; Yang Wan; Young-Joon Lee; Debabrata Mohapatra; Hong Wang; Greg Taylor; Devang Jariwala; Vijay Pitchumani; Patrick Morrow; Clair Webb; Paul Fischer; et al. (CICC, 2013)