Impact of Negative Bias Temperature Instability on Product Parametric Drift. - Vijay Reddy; John M. Carulli; Anand T. Krishnan; William Bosch; Brendan Burgess (ITC, 2004)

Impact of negative bias temperature instability on digital circuit reliability. - Vijay Reddy; Anand T. Krishnan; Andrew Marshall; John Rodriguez; Sreedhar Natarajan; Tim Rost; Srikanth Krishnan (Microelectron. Reliab., 2005)

Gate oxide failures due to anomalous stress from HBM ESD testers. - Charvaka Duvvury; Robert Steinhoff; Gianluca Boselli; Vijay Reddy; Hans Kunz; Steve Marum; Roger Cline (Microelectron. Reliab., 2006)

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. - Wenping Wang 004; Vijay Reddy; Anand T. Krishnan; Rakesh Vattikonda; Srikanth Krishnan; Yu Cao 001 (CICC, 2007)

Statistical prediction of circuit aging under process variations. - Wenping Wang 004; Vijay Reddy; Bo Yang; Varsha Balakrishnan; Srikanth Krishnan; Yu Cao 001 (CICC, 2008)

Circuit aging prediction for low-power operation. - Rui Zheng; Jyothi Velamala; Vijay Reddy; Varsha Balakrishnan; Evelyn Mintarno; Subhasish Mitra; Srikanth Krishnan; Yu Cao 001 (CICC, 2009)

Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors. - Min Chen 024; Vijay Reddy; Srikanth Krishnan; Venkatesh Srinivasan; Yu Cao 001 (IEEE Des. Test Comput., 2012)

ACE: A robust variability and aging sensor for high-k/metal gate SoC. - Min Chen 024; Vijay Reddy; Srikanth Krishnan; Jay Ondrusek; Yu Cao 001 (ESSDERC, 2013)

Performance entitlement by exploiting transistor's BTI recovery. - Senthil Arasu; Mehrdad Nourani; Vijay Reddy; John M. Carulli (ISQED, 2013)

A design-for-reliability approach based on grading library cells for aging effects. - Senthil Arasu; Mehrdad Nourani; John M. Carulli; Kenneth M. Butler; Vijay Reddy (ITC, 2013)

Asymmetric aging of clock networks in power efficient designs. - Senthil Arasu; Mehrdad Nourani; Frank Cano; John M. Carulli; Vijay Reddy (ISQED, 2014)

Reliability improvement of logic and clock paths in power-efficient designs. - Senthil Arasu; Mehrdad Nourani; Vijay Reddy; John M. Carulli Jr.; Gautam Kapila; Min Chen 024 (ACM J. Emerg. Technol. Comput. Syst., 2014)

Recovery modeling of negative bias temperature instability (NBTI) for SPICE-compatible circuit aging simulators. - Haldun Küflüoglu; Cathy Chancellor; Min Chen 024; Claude Cirba; Vijay Reddy (ACM J. Emerg. Technol. Comput. Syst., 2014)

Controlling Aging in Timing-Critical Paths. - Senthil Arasu; Mehrdad Nourani; John M. Carulli; Vijay Reddy (IEEE Des. Test, 2016)

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. - Gyusung Park; Minsu Kim; Chris H. Kim; Bongjin Kim; Vijay Reddy (IRPS, 2018)

Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process. - Nakul Pande; Gyusung Park; Chris H. Kim; Srikanth Krishnan; Vijay Reddy (IRPS, 2019)

A Novel 'I-V Spectroscopy' Technique to Deconvolve Threshold Voltage and Mobility Degradation in LDMOS Transistors. - Yen-Pu Chen; Bikram Kishore Mahajan; Dhanoop Varghese; Srikanth Krishnan; Vijay Reddy; Muhammad Ashraful Alam (IRPS, 2020)

Quantifying Region-Specific Hot Carrier Degradation in LDMOS Transistors Using a Novel Charge Pumping Technique. - Bikram Kishore Mahajan; Yen-Pu Chen; Dhanoop Varghese; Vijay Reddy; Srikanth Krishnan; Muhammad Ashraful Alam (IRPS, 2021)

A Critical Examination of the TCAD Modeling of Hot Carrier Degradation for LDMOS Transistors. - Bikram Kishore Mahajan; Yen-Pu Chen; Muhammad Ashraful Alam; Dhanoop Varghese; Srikanth Krishnan; Vijay Reddy (IRPS, 2022)

Positive Bias Temperature Instability in Polysilicon/SiO2 PMOS Transistors for Analog High Precision Applications. - Dhanoop Varghese; Vijaya Vemuri; Arif Sonnet; Vijay Reddy; Srikanth Krishnan; Vivek Varier; Cheuk Yu; Srinivas Pulijala (IRPS, 2025)