Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units. - Vijay S. Iyengar; Larry L. Kinney (ITC, 1982)

Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. - Zeev Barzilai; Vijay S. Iyengar; Barry K. Rosen; Gabriel M. Silberman (ITC, 1985)

Concurrent Fault Detection in Microprogrammed Control Units. - Vijay S. Iyengar; Larry L. Kinney (IEEE Trans. Computers, 1985)

SLS - a fast switch level simulator for verification and fault coverage analysis. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (DAC, 1986)

Efficient Fault Simulation of CMOS Circuits with Accurate Models. - Zeev Barzilai; J. Lawrence Carter; Vijay S. Iyengar; Indira Nair; Barry K. Rosen; Joe D. Rutledge; Gabriel M. Silberman (ITC, 1986)

Transition Fault Simulation by Parallel Pattern Single Fault Propagation. - John A. Waicukauski; Eric Lindbloom; Vijay S. Iyengar; Barry K. Rosen (ITC, 1986)

Transition Fault Simulation. - John A. Waicukauski; Eric Lindbloom; Barry K. Rosen; Vijay S. Iyengar (IEEE Des. Test, 1987)

On simulating faults in parallel. - Vijay S. Iyengar; Donald T. Tang (FTCS, 1988)

Delay Test Generation 1: Concepts and Coverage Metrics. - Vijay S. Iyengar; Barry K. Rosen; Ilan Y. Spillinger (ITC, 1988)

Delay Test Generation 2: Algebra and Algorithms. - Vijay S. Iyengar; Barry K. Rosen; Ilan Y. Spillinger (ITC, 1988)

Timing Analysis Using Functional Analysis. - Daniel Brand; Vijay S. Iyengar (IEEE Trans. Computers, 1988)

SLS-a fast switch-level simulator [for MOS]. - Zeev Barzilai; Daniel K. Beece; Leendert M. Huisman; Vijay S. Iyengar; Gabriel M. Silberman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Synthesis of Pseudo-Random Pattern Testable Designs. - Daniel Brand; Vijay S. Iyengar (ITC, 1989)

On computing the sizes of detected delay faults. - Vijay S. Iyengar; Barry K. Rosen; John A. Waicukauski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Symbolic implication in test generation. - Sandip Kundu; Indira Nair; Leendert M. Huisman; Vijay S. Iyengar (EURO-DAC, 1991)

Test Application Timing: The Unexplored Issue in AC Test. - Vijay S. Iyengar; Gopalakrishnan Vijayan (ITC, 1991)

Identification of Single Gate Delay Fault Redundancies. - Daniel Brand; Vijay S. Iyengar (ICCD, 1992)

Constraint Slving for Test Case Generation. - Ashok K. Chandra; Vijay S. Iyengar (ICCD, 1992)

AC Test Quality: Beyond Transition Fault Coverage. - Yaron Aizenbud; Paul Chang; Moshe Leibowitz; Dave Smith; Bernd Könemann; Vijay S. Iyengar; Barry K. Rosen (ITC, 1992)

Delay Test: The Next Frontier for LSSD Test Systems. - Bernd Könemann; J. Barlow; Paul Chang; R. Gabrielson; C. Goertz; Brion L. Keller; Kevin McCauley; J. Tischer; Vijay S. Iyengar; Barry K. Rosen; T. Williams (ITC, 1992)

A Small Test Generator for Large Designs. - Sandip Kundu; Leendert M. Huisman; Indira Nair; Vijay S. Iyengar; Lakshmi N. Reddy (ITC, 1992)

Optimized test application timing for AC test. - Vijay S. Iyengar; Gopalakrishnan Vijayan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Architectural Verification of Processors Using Symbolic Instruction Graphs. - Ashok K. Chandra; Vijay S. Iyengar; R. V. Jawalekar; Michael P. Mullen; Indira Nair; Barry K. Rosen (ICCD, 1994)

Identification of redundant delay faults. - Daniel Brand; Vijay S. Iyengar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

AVPGEN-A test generator for architecture verification. - Ashok K. Chandra; Vijay S. Iyengar; D. Jameson; R. V. Jawalekar; Indira Nair; Barry K. Rosen; Michael P. Mullen; J. Yoon; R. Armoni; Daniel Geist; Yaron Wolfsthal (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Representative Traces for Processor Models with Infinite Cache. - Vijay S. Iyengar; Louise Trevillyan; Pradip Bose (HPCA, 1996)

HOT: Heuristics for Oblique Trees. - Vijay S. Iyengar (ICTAI, 1999)

Active learning using adaptive resampling. - Vijay S. Iyengar; Chidanand Apté; Tong Zhang 001 (KDD, 2000)

Texture-space segmentation and multi-resolution mapping for forestry applications. - Matthew L. Hill; Yuan-Chi Chang; Vijay S. Iyengar; Chung-Sheng Li (ICASSP, 2001)

Empirical Study of Recommender Systems Using Linear Classifiers. - Vijay S. Iyengar; Tong Zhang 001 (PAKDD, 2001)

Evaluating multiple attribute items using queries. - Vijay S. Iyengar; Jon Lee 001; Murray Campbell (EC, 2001)

Transforming data to satisfy privacy constraints. - Vijay S. Iyengar (KDD, 2002)

Recommender Systems Using Linear Classifier. - Tong Zhang 001; Vijay S. Iyengar (J. Mach. Learn. Res., 2002)

Epi-SPIRE: a system for environmental and public health activity monitoring. - Chung-Sheng Li; Charu C. Aggarwal; Murray Campbell; Yuan-Chi Chang; Gregory Glass; Vijay S. Iyengar; Mahesh Joshi; Ching-Yung Lin; Milind R. Naphade; John R. Smith; Belle L. Tseng; Min Wang 001; et al. (ICME, 2003)

On detecting space-time clusters. - Vijay S. Iyengar (KDD, 2004)

Evaluation of IT Portfolio Options by Linking to Business Services. - Vijay S. Iyengar; David Flaxer; Anil Nigam; John Vergo (DEECS, 2006)

Analytics for Audit and Business Controls in Corporate Travel and Entertainment. - Vijay S. Iyengar; Ioana Boier; Karen Kelley; Raymond Curatolo (AusDM, 2007)

Event detection in sensor networks for modern oil fields. - Matthew L. Hill; Murray Campbell; Yuan-Chi Chang; Vijay S. Iyengar (DEBS, 2008)

A configurable, big data system for on-demand healthcare cost prediction. - Karthikeyan Natesan Ramamurthy; Dennis Wei; Emily Ray; Moninder Singh; Vijay S. Iyengar; Dmitriy A. Katz-Rogozhnikov; Jingwei Yang; Kevin N. Tran; Gigi Y. Yuen-Reed (IEEE BigData, 2017)

TIP: Typifying the Interpretability of Procedures. - Amit Dhurandhar; Vijay S. Iyengar; Ronny Luss; Karthikeyan Shanmugam (CoRR, 2017)

A Formal Framework to Characterize Interpretability of Procedures. - Amit Dhurandhar; Vijay S. Iyengar; Ronny Luss; Karthikeyan Shanmugam (CoRR, 2017)

Confidence Scoring Using Whitebox Meta-models with Linear Classifier Probes. - Tongfei Chen; Jirí Navrátil 001; Vijay S. Iyengar; Karthikeyan Shanmugam (AISTATS, 2019)