A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers. - Michael E. Zervakis; Vijay Sundararajan; Keshab K. Parhi (ICIP (1), 1997)

Synthesis of folded, pipelined architectures for multi-dimensional multirate systems. - Vijay Sundararajan; Keshab K. Parhi (ICASSP, 1998)

Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. - Vijay Sundararajan; Keshab K. Parhi (ARVLSI, 1999)

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. - Vijay Sundararajan; Keshab K. Parhi (DAC, 1999)

Marsh: min-area retiming with setup and hold constraints. - Vijay Sundararajan; Sachin S. Sapatnekar; Keshab K. Parhi (ICCAD, 1999)

Low power synthesis of dual threshold voltage CMOS VLSI circuits. - Vijay Sundararajan; Keshab K. Parhi (ISLPED, 1999)

Synthesis of low power folded programmable coefficient FIR digital filters (short paper). - Vijay Sundararajan; Keshab K. Parhi (ASP-DAC, 2000)

Data transmission over a bus with peak-limited transition activity. - Vijay Sundararajan; Keshab K. Parhi (ASP-DAC, 2000)

MINFLOTRANSIT: min-cost flow based transistor sizing tool. - Vijay Sundararajan; Sachin S. Sapatnekar; Keshab K. Parhi (DAC, 2000)

Reducing bus transition activity by limited weight coding with codeword slimming. - Vijay Sundararajan; Keshab K. Parhi (ACM Great Lakes Symposium on VLSI, 2000)

A novel multiply multiple accumulator component for low power PDSP design. - Vijay Sundararajan; Keshab K. Parhi (ICASSP, 2000)

Energy efficient signaling in DSM CMOS technology. - Imed Ben Dhaou; Hannu Tenhunen; Vijay Sundararajan; Keshab K. Parhi (ISCAS (5), 2001)

Energy Efficient Signaling in Deep Submicron CMOS Technology. - Imed Ben Dhaou; Hannu Tenhunen; Vijay Sundararajan; Keshab K. Parhi (ISQED, 2001)

Vector processing of wavelet coefficients for robust image denoising. - Michael E. Zervakis; Vijay Sundararajan; Keshab K. Parhi (Image Vis. Comput., 2001)

Fast and exact transistor sizing based on iterative relaxation. - Vijay Sundararajan; Sachin S. Sapatnekar; Keshab K. Parhi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems. - Vijay Sundararajan; Keshab K. Parhi (IEEE Trans. Signal Process., 2003)

A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. - Vijay Sundararajan; Sachin S. Sapatnekar; Keshab K. Parhi (ACM Trans. Design Autom. Electr. Syst., 2004)

Optimal power allocation for sum capacity of a slotted three-cell system. - Vikram Chandrasekhar; Zukang Shen; Vijay Sundararajan (ICASSP, 2008)

Gate Sizing. - Vijay Sundararajan (Encyclopedia of Algorithms, 2008)

Gate Sizing. - Vijay Sundararajan (Encyclopedia of Algorithms, 2016)