Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. - T. Venkata Kalyan; Madhu Mutyam; Vijaya Sankara Rao Pasupureddi (VLSI Design, 2008)

High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect. - Vijaya Sankara Rao Pasupureddi; Pradip Mandal; Sunil Sachdev (ISVLSI, 2009)

Current-mode echo cancellation for full-duplex chip-to-chip data communication. - Vijaya Sankara Rao Pasupureddi; Pradip Mandal (APCCAS, 2010)

A new power efficient current-mode 4-PAM transmitter interface for off-chip interconnect. - Vijaya Sankara Rao Pasupureddi; Pradip Mandal (APCCAS, 2010)

A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture. - Mrigank Sharad; Vijaya Sankara Rao Pasupureddi; Pradip Mandal (VLSI Design, 2011)

Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect. - Vijaya Sankara Rao Pasupureddi; Pradip Mandal (Microelectron. J., 2011)

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination. - Vijaya Sankara Rao Pasupureddi; Nachiket V. Desai; Pradip Mandal (Circuits Syst. Signal Process., 2012)

Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling. - Vijaya Sankara Rao Pasupureddi; Pradip Mandal (Int. J. Circuit Theory Appl., 2012)

A low-power area-efficient compressive sensing approach for multi-channel neural recording. - Mahsa Shoaran; Mariazel Maqueda Lopez; Vijaya Sankara Rao Pasupureddi; Yusuf Leblebici; Alexandre Schmid (ISCAS, 2013)

Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy. - Bhuvanan Kaliannan; Vijaya Sankara Rao Pasupureddi (VLSI Design, 2013)

100-Mbps transceiver for enhanced MIL-STD-1553. - Divya Duvvuri; Vijaya Sankara Rao Pasupureddi; J. Chattopadhyay (APCCAS, 2014)

Design and simulation of a wideband channelized transceiver for DRFM applications. - Ajinkya Kale; Vijaya Sankara Rao Pasupureddi; J. Chattopadhyay (APCCAS, 2014)

A 5-Gb/s adaptive CTLE with eye-monitoring for multi-drop bus applications. - Somanshu Agarwal; Vijaya Sankara Rao Pasupureddi (MWSCAS, 2014)

A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source. - R. Gopikrishnan; Vijaya Sankara Rao Pasupureddi; Govindarajulu Regeti (VLSID, 2014)

A Low Power CMOS Imager Based on Distributed Compressed Sensing. - Bhuvanan Kaliannan; Vijaya Sankara Rao Pasupureddi (VLSID, 2014)

MIL-STD-1553+: Integrated remote terminal and bus controller at 100-Mb/s data rate. - Prateek Pendyala; Vijaya Sankara Rao Pasupureddi (ISCAS, 2015)

RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate. - Prateek Pendyala; Vijaya Sankara Rao Pasupureddi (ISQED, 2015)

A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receivers. - Suchendranath Popuri; Vijaya Sankara Rao Pasupureddi; Johannes Sturm (ESSCIRC, 2016)

A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects. - Divya Duvvuri; Somanshu Agarwal; Vijaya Sankara Rao Pasupureddi (ISCAS, 2016)

A low power charge mode compressive acquisition of multichannel EEG signals. - Bhuvanan Kaliannan; Vijaya Sankara Rao Pasupureddi (ISCAS, 2016)

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation. - Divya Duvvuri; Vijaya Sankara Rao Pasupureddi (ISVLSI, 2016)

Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate. - Prateek Pendyala; Vijaya Sankara Rao Pasupureddi (VDAT, 2016)

Design and analysis of a current mode integrated CTLE with charge mode adaptation. - Divya Duvvuri; Vijaya Sankara Rao Pasupureddi (Microelectron. J., 2016)

100-Mb/s enhanced data rate MIL-STD-1553B controller in 65-nm CMOS technology. - Prateek Pendyala; Vijaya Sankara Rao Pasupureddi (IEEE Trans. Aerosp. Electron. Syst., 2016)

0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR. - Ajinkya Kale; Johannes Sturm; Vijaya Sankara Rao Pasupureddi (ISVLSI, 2018)

Integration solutions for reconfigurable multi-standard wireless transceivers. - Ajinkya Kale; Graciele Batistell; Suchendranath Popuri; Vijaya Sankara Rao Pasupureddi; Wolfgang Bösch; Johannes Sturm (Elektrotech. Informationstechnik, 2018)

A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. - Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (VDAT, 2019)

A -40-dB EVM 20-MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization. - Ajinkya Kale; Johannes Sturm; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2019)

A -40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS. - Ajinkya Kale; Suchendranath Popuri; Michael Koeberle; Johannes Sturm; Vijaya Sankara Rao Pasupureddi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects. - Pankaj Venuturupalli; Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (ISCAS, 2020)

A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS. - Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (ISVLSI, 2020)

Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS. - Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2020)

Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects. - Pankaj Venuturupalli; Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (Microelectron. J., 2020)

A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End. - Rakesh Rena; Suraj Kumar Verma; Vijaya Sankara Rao Pasupureddi (ISCAS, 2021)

A 27-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS. - Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (Circuits Syst. Signal Process., 2021)

Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects. - Prema Kumar Govindaswamy; Nijwm Wary; Vijaya Sankara Rao Pasupureddi (ISCAS, 2022)

A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects. - Prema Kumar Govindaswamy; Nijwm Wary; Vijaya Sankara Rao Pasupureddi (ISCAS, 2022)

Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture. - Rakesh Rena; Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (MWSCAS, 2022)

A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects. - Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2022)

A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS. - Raviteja Kammari; Sarvesh Rajesh Tuckely; Vijay Shankar Pasupureddi (APCCAS, 2023)

0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS. - Rakesh Varma Rena; Raviteja Kammari; Vijay Shankar Pasupureddi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects. - Prema Kumar Govindaswamy; Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2023)

A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS. - Perakalapudi Ravibabu; Prema Kumar Govindaswamy; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISQED, 2024)

A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology. - Srinivasa Rao Maram; Subrahmanyam Boyapati; Vijay Shankar Pasupureddi (ISQED, 2024)

A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End. - Rakesh Varma Rena; Raviteja Kammari; Vijay Shankar Pasupureddi (IEEE Trans. Very Large Scale Integr. Syst., 2024)

3.6-pJ/Spike, 30-Hz Silicon Neuron Circuit in 0.5-V, 65-nm CMOS for Spiking Neural Networks. - Srikanth Vuppunuthala; Vijay Shankar Pasupureddi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Breaking the Trade-off Between Input Impedance and Mixer Paths in Sub-Harmonic N-Path Mixer-First RF Front-end. - Raviteja Kammari; Vijay Shankar Pasupureddi (ISCAS, 2025)

A ±0.6 dB, 256-μW Digital-Intensive RSSI with 80-dB Dynamic-Range in 65-nm CMOS. - Sivaiah Naali; Ravi Prakash Bisen; Raviteja Kammari; Vijay Shankar Pasupureddi (ISCAS, 2025)

350-fJ/spike, 30-Hz Bio-inspired Silicon Neuron Circuit in 0.2 V, 65 nm CMOS. - Sivaiah Naali; Srikanth Vuppunuthala; Vijay Shankar Pasupureddi (ISCAS, 2025)

A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS. - Prema Kumar Govindaswamy; Nijwm Wary; Vijay Shankar Pasupureddi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)