Towards a Communication Characterization Methodology for Parallel Applications. - Sucheta Chodnekar; Viji Srinivasan; Aniruddha S. Vaidya; Anand Sivasubramaniam; Chita R. Das (HPCA, 1997)

Evaluating the performance of active cache management schemes. - Edward S. Tam; Jude A. Rivers; Vijayalakshmi Srinivasan; Gary S. Tyson; Edward S. Davidson (ICCD, 1998)

Active Management of Data Caches by Exploiting Reuse Information. - Edward S. Tam; Jude A. Rivers; Vijayalakshmi Srinivasan; Gary S. Tyson; Edward S. Davidson (IEEE Trans. Computers, 1999)

Branch History Guided Instruction Prefetching. - Viji Srinivasan; Edward S. Davidson; Gary S. Tyson; Mark J. Charney; Thomas R. Puzak (HPCA, 2001)

Hardware solutions to reduce effective memory access time. - Vijayalakshmi Srinivasan (2001)

Optimizing pipelines for power and performance. - Viji Srinivasan; David M. Brooks; Michael Gschwind; Pradip Bose; Victor V. Zyuban; Philip N. Strenski; Philip G. Emma (MICRO, 2002)

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. - Pradip Bose; David M. Brooks; Alper Buyuktosunoglu; Peter W. Cook; K. Das; Philip G. Emma; Michael Gschwind; Hans M. Jacobson; Tejas Karkhanis; Prabhakar Kudva; Stanley Schuster; James E. Smith 001; et al. (PACS, 2002)

Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. - Rajeev Balasubramonian; Viji Srinivasan; Sandhya Dwarkadas; Alper Buyuktosunoglu (PACS, 2003)

New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. - David M. Brooks; Pradip Bose; Viji Srinivasan; Michael Gschwind; Philip G. Emma; Michael G. Rosenfield (IBM J. Res. Dev., 2003)

Microarchitectural techniques for power gating of execution units. - Zhigang Hu; Alper Buyuktosunoglu; Viji Srinivasan; Victor V. Zyuban; Hans M. Jacobson; Pradip Bose (ISLPED, 2004)

A Prefetch Taxonomy. - Viji Srinivasan; Edward S. Davidson; Gary S. Tyson (IEEE Trans. Computers, 2004)

Integrated Analysis of Power and Performance for Pipelined Microprocessors. - Victor V. Zyuban; David M. Brooks; Viji Srinivasan; Michael Gschwind; Pradip Bose; Philip N. Strenski; Philip G. Emma (IEEE Trans. Computers, 2004)

When prefetching improves/degrades performance. - Thomas R. Puzak; Allan Hartstein; Philip G. Emma; Viji Srinivasan (Conf. Computing Frontiers, 2005)

Exploring the limits of prefetching. - Philip G. Emma; Allan Hartstein; Thomas R. Puzak; Viji Srinivasan (IBM J. Res. Dev., 2005)

Cache miss behavior: is it sqrt(2)? - Allan Hartstein; Viji Srinivasan; Thomas R. Puzak; Philip G. Emma (Conf. Computing Frontiers, 2006)

An analysis of the effects of miss clustering on the cost of a cache miss. - Thomas R. Puzak; Allan Hartstein; Philip G. Emma; Viji Srinivasan; Jim Mitchell (Conf. Computing Frontiers, 2007)

Pipeline spectroscopy. - Thomas R. Puzak; Allan Hartstein; Philip G. Emma; Viji Srinivasan; Arthur Nadas (Experimental Computer Science, 2007)

On the Nature of Cache Miss Behavior: Is It √2? - Allan Hartstein; Vijayalakshmi Srinivasan; Thomas R. Puzak; Philip G. Emma (J. Instr. Level Parallelism, 2008)

Analyzing the Cost of a Cache Miss Using Pipeline Spectroscopy. - Thomas R. Puzak; Allan Hartstein; Philip G. Emma; Vijayalakshmi Srinivasan; Arthur Nadas (J. Instr. Level Parallelism, 2008)

Scalable high performance main memory system using phase-change memory technology. - Moinuddin K. Qureshi; Vijayalakshmi Srinivasan; Jude A. Rivers (ISCA, 2009)

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. - Moinuddin K. Qureshi; John P. Karidis; Michele Franceschini; Vijayalakshmi Srinivasan; Luis A. Lastras; Bülent Abali (MICRO, 2009)

A tagless coherence directory. - Jason Zebchuk; Vijayalakshmi Srinivasan; Moinuddin K. Qureshi; Andreas Moshovos (MICRO, 2009)

SAFER: Stuck-At-Fault Error Recovery for Memories. - Nak Hee Seong; Dong Hyuk Woo; Vijayalakshmi Srinivasan; Jude A. Rivers; Hsien-Hsin S. Lee (MICRO, 2010)

SPATL: Honey, I Shrunk the Coherence Directory. - Hongzhou Zhao; Arrvindh Shriraman; Sandhya Dwarkadas; Vijayalakshmi Srinivasan (PACT, 2011)

Big Chips. - Andrew B. Kahng; Vijayalakshmi Srinivasan (IEEE Micro, 2011)

ReCaP: a region-based cure for the common cold cache. - Jason Zebchuk; Harold W. Cain; Vijayalakshmi Srinivasan; Andreas Moshovos (PACT, 2012)

Efficient scrub mechanisms for error-prone emerging memories. - Manu Awasthi; Manjunath Shevgoor; Kshitij Sudan; Bipin Rajendran; Rajeev Balasubramonian; Viji Srinivasan (HPCA, 2012)

Programming with relaxed synchronization. - Lakshminarayanan Renganarayana; Vijayalakshmi Srinivasan; Ravi Nair; Daniel A. Prener (RACES@SPLASH, 2012)

RECAP: A region-based cure for the common cold (cache). - Jason Zebchuk; Harold W. Cain; Xin Tong 005; Vijayalakshmi Srinivasan; Andreas Moshovos (HPCA, 2013)

SQRL: hardware accelerator for collecting software data structures. - Snehasish Kumar; Arrvindh Shriraman; Vijayalakshmi Srinivasan; Dan Lin 003; Jordon Phillips (PACT, 2014)

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads. - Seth H. Pugsley; Jeffrey Jestes; Huihui Zhang; Rajeev Balasubramonian; Vijayalakshmi Srinivasan; Alper Buyuktosunoglu; Al Davis; Feifei Li 001 (ISPASS, 2014)

Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads. - Seth H. Pugsley; Jeffrey Jestes; Rajeev Balasubramonian; Vijayalakshmi Srinivasan; Alper Buyuktosunoglu; Al Davis; Feifei Li 001 (IEEE Micro, 2014)

DASX: Hardware Accelerator for Software Data Structures. - Snehasish Kumar; Naveen Vedula; Arrvindh Shriraman; Vijayalakshmi Srinivasan (ICS, 2015)

Self-contained, accurate precomputation prefetching. - Islam Atta; Xin Tong 005; Vijayalakshmi Srinivasan; Ioana Baldini; Andreas Moshovos (MICRO, 2015)

Approximate computing: Challenges and opportunities. - Ankur Agrawal; Jungwook Choi; Kailash Gopalakrishnan; Suyog Gupta; Ravi Nair; Jinwook Oh; Daniel A. Prener; Sunil Shukla; Vijayalakshmi Srinivasan; Zehra Sura (ICRC, 2016)

Peruse and Profit: Estimating the Accelerability of Loops. - Snehasish Kumar; Vijayalakshmi Srinivasan; Amirali Sharifian; Nick Sumner; Arrvindh Shriraman (ICS, 2016)

Co-designing accelerators and SoC interfaces using gem5-Aladdin. - Yakun Sophia Shao; Sam Likun Xi; Vijayalakshmi Srinivasan; Gu-Yeon Wei; David M. Brooks (MICRO, 2016)

POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators. - Swagath Venkataramani; Jungwook Choi; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan; Leland Chang (PACT, 2017)

Accelerator Design for Deep Learning Training: Extended Abstract: Invited. - Ankur Agrawal; Chia-Yu Chen; Jungwook Choi; Kailash Gopalakrishnan; Jinwook Oh; Sunil Shukla; Viji Srinivasan; Swagath Venkataramani; Wei Zhang 022 (DAC, 2017)

Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs. - Snehasish Kumar; Nick Sumner; Vijayalakshmi Srinivasan; Steve Margerm; Arrvindh Shriraman (HPCA, 2017)

Special Issue on Network and Parallel Computing. - Vijayalakshmi Srinivasan; Yunquan Zhang (Int. J. Parallel Program., 2017)

Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. - Shubham Jain; Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Pierce Chuang; Leland Chang (DAC, 2018)

Exploiting approximate computing for deep learning acceleration. - Chia-Yu Chen; Jungwook Choi; Kailash Gopalakrishnan; Viji Srinivasan; Swagath Venkataramani (DATE, 2018)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

Taming the beast: Programming Peta-FLOP class Deep Learning Systems. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Kailash Gopalakrishnan; Leland Chang (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

PACT: Parameterized Clipping Activation for Quantized Neural Networks. - Jungwook Choi; Zhuo Wang; Swagath Venkataramani; Pierce I-Jen Chuang; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan (CoRR, 2018)

Bridging the Accuracy Gap for 2-bit Quantized Neural Networks (QNN). - Jungwook Choi; Pierce I-Jen Chuang; Zhuo Wang; Swagath Venkataramani; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan (CoRR, 2018)

A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel. - Eri Ogawa; Kazuaki Ishizaki; Hiroshi Inoue; Swagath Venkataramani; Jungwook Choi; Wei Wang 333; Vijayalakshmi Srinivasan; Moriyoshi Ohara; Kailash Gopalakrishnan (COOL CHIPS, 2019)

BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks. - Shubham Jain; Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Kailash Gopalakrishnan; Leland Chang (DAC, 2019)

Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Jungwook Choi; Philip Heidelberger; Leland Chang; Kailash Gopalakrishnan (HiPC, 2019)

Workload-aware Automatic Parallelization for Multi-GPU DNN Training. - Sungho Shin; Youngmin Jo; Jungwook Choi; Swagath Venkataramani; Vijayalakshmi Srinivasan; Wonyong Sung (ICASSP, 2019)

Performance-driven Programming of Multi-TFLOP Deep Learning Accelerators. - Swagath Venkataramani; Jungwook Choi; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan; Leland Chang (IISWC, 2019)

Accurate and Efficient 2-bit Quantized Neural Networks. - Jungwook Choi; Swagath Venkataramani; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan; Zhuo Wang; Pierce Chuang (SysML, 2019)

Hybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networks. - Xiao Sun 013; Jungwook Choi; Chia-Yu Chen; Naigang Wang; Swagath Venkataramani; Vijayalakshmi Srinivasan; Xiaodong Cui; Wei Zhang 022; Kailash Gopalakrishnan (NeurIPS, 2019)

DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator. - Swagath Venkataramani; Jungwook Choi; Vijayalakshmi Srinivasan; Wei Wang 333; Jintao Zhang; Marcel Schaal; Mauricio J. Serrano; Kazuaki Ishizaki; Hiroshi Inoue; Eri Ogawa; Moriyoshi Ohara; Leland Chang; et al. (IEEE Micro, 2019)

ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training. - Chia-Yu Chen; Jiamin Ni; Songtao Lu; Xiaodong Cui; Pin-Yu Chen; Xiao Sun 013; Naigang Wang; Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Zhang 022; Kailash Gopalakrishnan (NeurIPS, 2020)

Ultra-Low Precision 4-bit Training of Deep Neural Networks. - Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jiamin Ni; Ankur Agrawal; Xiaodong Cui; Swagath Venkataramani; Kaoutar El Maghraoui; Vijayalakshmi Srinivasan; Kailash Gopalakrishnan (NeurIPS, 2020)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. - Subhankar Pal; Swagath Venkataramani; Viji Srinivasan; Kailash Gopalakrishnan (ISPASS, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

Deep Compression of Pre-trained Transformer Models. - Naigang Wang; Chi-Chun (Charlie) Liu; Swagath Venkataramani; Sanchari Sen; Chia-Yu Chen; Kaoutar El Maghraoui; Vijayalakshmi Srinivasan; Leland Chang (NeurIPS, 2022)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators. - Subhankar Pal; Swagath Venkataramani; Viji Srinivasan; Kailash Gopalakrishnan (ACM Trans. Embed. Comput. Syst., 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU. - Sanchari Sen; Shubham Jain; Sarada Krithivasan; Swagath Venkataramani; Vijayalakshmi Srinivasan (IEEE Micro, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)