A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. - Alan J. Drake; Robert M. Senger; Harmander Deogun; Gary D. Carpenter; Soraya Ghiasi; Tuyet Nguyen; Norman K. James; Michael S. Floyd; Vikas Pokala (ISSCC, 2007)

Soft-error resilience of the IBM POWER6 processor input/output subsystem. - Carl A. Bender; Pia N. Sanda; Prabhakar Kudva; Ricardo Mata; Vikas Pokala; Ryan Haraden; Matthew Schallhorn (IBM J. Res. Dev., 2008)