A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders. - Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz (ICME, 2011)

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm. - Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz (J. Networks, 2011)

VLSI Design - A Practical Guide for FPGA and ASIC Implementations - Vikram Arkalgud Chandrasetty (Springer, 2011)

An area efficient LDPC decoder using a reduced complexity min-sum algorithm. - Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz (Integr., 2012)

A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation. - Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz (J. Networks, 2012)

Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes - Vikram Arkalgud Chandrasetty; Sarah J. Johnson; Gottfried Lechner (CoRR, 2013)

Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes. - Vikram Arkalgud Chandrasetty; Sarah J. Johnson; Gottfried Lechner (IET Commun., 2014)

Resource efficient LDPC decoders for multimedia communication. - Vikram Arkalgud Chandrasetty; Syed Mahfuzul Aziz (Integr., 2015)

Repeat-accumulate codes for reconciliation in continuous variable quantum key distribution. - Sarah J. Johnson; Vikram Arkalgud Chandrasetty; Andrew M. Lance (AusCTW, 2016)