Entropy Extraction in Metastability-based TRNG. - Vikram B. Suresh; Wayne P. Burleson (HOST, 2010)

Implementing hardware Trojans: Experiences from a hardware Trojan challenge. - Georg T. Becker; Ashwin Lakshminarasimhan; Lang Lin; Sudheendra Srivathsa; Vikram B. Suresh; Wayne P. Burleson (ICCD, 2011)

On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. - Vikram B. Suresh; Priyamvada Vijayakumar; Sandip Kundu (ISVLSI, 2011)

Lithography aware critical area estimation and yield analysis. - Priyamvada Vijayakumar; Vikram B. Suresh; Sandip Kundu (ITC, 2011)

Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration. - Vikram B. Suresh; Wayne P. Burleson (ISQED, 2012)

On lithography aware metal-fill insertion. - Vikram B. Suresh; Priyamvada Vijayakumar; Sandip Kundu (ISQED, 2012)

On-chip lightweight implementation of reduced NIST randomness test suite. - Vikram B. Suresh; Daniele Antonioli; Wayne P. Burleson (HOST, 2013)

Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array. - Vikram B. Suresh; Sandip Kundu (ICCD, 2013)

On analyzing and mitigating SRAM BER due to random thermal noise. - Vikram B. Suresh; Sandip Kundu (ISVLSI, 2013)

Design of 8T-nanowire RAM array. - Vikram B. Suresh; Akshaya Shanmugam; Lekshmi Krishnan; Avinash Bijjal; Mostafizur Rahman; Csaba Andras Moritz (NANOARCH, 2013)

Fine grained wearout sensing using metastability resolution time. - Vikram B. Suresh; Wayne P. Burleson (ISQED, 2014)

Variation Aware Design of Post-Silicon Tunable Clock Buffer. - Vikram B. Suresh; Wayne P. Burleson (ISVLSI, 2014)

Post-Silicon Validation and Calibration of Hardware Security Primitives. - Xiaolin Xu 001; Vikram B. Suresh; Raghavan Kumar; Wayne P. Burleson (ISVLSI, 2014)

REFLEX: Reconfigurable logic for entropy extraction. - Vikram B. Suresh; Wayne P. Burleson (SoCC, 2014)

340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Himanshu Kaul; Mark A. Anders 001; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSIC, 2014)

μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. - Sanu Mathew; David Johnston; Paul Newman 002; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Gregory K. Chen; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2015)

340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001 (IEEE J. Solid State Circuits, 2015)

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing. - Vikram B. Suresh; Wayne P. Burleson (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Gregory K. Chen; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De (A-SSCC, 2016)

Ultra-low energy security circuits for IoT applications. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Ram Krishnamurthy 001 (ICCD, 2016)

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2016)

250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001 (VLSI Circuits, 2016)

µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. - Sanu K. Mathew; David Johnston; Sudhir Satpathy; Vikram B. Suresh; Paul Newman 002; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2016)

Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array. - Vikram B. Suresh; Sandip Kundu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Ram K. Krishnamurthy (CICC, 2017)

Invited paper: Ultra-low energy security circuit primitives for IoT platforms. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Ram Krishnamurthy 001 (ISLPED, 2017)

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. - Sudhir Satpathy; Sanu K. Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek K. De (IEEE J. Solid State Circuits, 2017)

Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Vikram B. Suresh; Sudhir Satpathy; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (A-SSCC, 2018)

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (A-SSCC, 2018)

Ultra-low energy circuit building blocks for security technologies. - Sanu Mathew; Sudhir Satpathy; Vikram B. Suresh; Ram Krishnamurthy 001 (DATE, 2018)

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Kam Krisnnamurthy (ESSCIRC, 2018)

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. - Vikram B. Suresh; Sudhir Satpathy; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (ESSCIRC, 2018)

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. - Mark A. Anders 001; Himanshu Kaul; Sanu Mathew; Vikram B. Suresh; Sudhir Satpathy; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSI Circuits, 2018)

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. - Sudhir Satpathy; Sanu Mathew; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2018)

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. - Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001 (VLSI Circuits, 2018)

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. - Amit Agarwal 001; Steven Hsu; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (A-SSCC, 2019)

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. - Sudhir Satpathy; Vikram B. Suresh; Raghavan Kumar; Vinodh Gopal; James Guilford; Kirk Yap; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Sanu Mathew (CICC, 2019)

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. - Vikram B. Suresh; Sudhir Satpathy; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Sanu Mathew (CICC, 2019)

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. - Steven Hsu; Amit Agarwal 001; Monodeep Kar; Mark A. Anders 001; Himanshu Kaul; Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Sanu Mathew; Ram Krishnamurthy 001; Vivek De (VLSI Circuits, 2019)

A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. - Sudhir Satpathy; Vikram B. Suresh; Raghavan Kumar; Vinodh Gopal; James Guilford; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. - Vikram B. Suresh; Sudhir Satpathy; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram Krishnamurthy 001; Vivek De; Sanu Mathew (VLSI Circuits, 2019)

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. - Sudhir Satpathy; Sanu K. Mathew; Raghavan Kumar; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Ram K. Krishnamurthy; Vivek De (IEEE J. Solid State Circuits, 2019)

INVITED: A 0.26% BER, Machine-Learning Resistant 1028 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. - Vikram B. Suresh; Raghavan Kumar; Sanu Mathew (DAC, 2020)

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. - Mark A. Anders 001; Himanshu Kaul; Seongjong Kim; Gregory K. Chen; Raghavan Kumar; Huseyin Ekin Sumbul; Phil C. Knag; Monodeep Kar; Steven K. Hsu; Amit Agarwal 001; Vikram B. Suresh; Sanu K. Mathew; et al. (ISSCC, 2020)

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. - Steven Hsu; Amit Agarwal 001; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Vikram B. Suresh; Sanu Mathew; et al. (VLSI Circuits, 2020)

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish Krishnamurthy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. - Raghavan Kumar; Sudhir Satpathy; Vikram B. Suresh; Mark A. Anders 001; Himanshu Kaul; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. - Vikram B. Suresh; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A 4900- $ mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. - Raghavan Kumar; Vikram B. Suresh; Monodeep Kar; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Amit Agarwal 001; Steven Hsu; Gregory K. Chen; Ram K. Krishnamurthy; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2020)

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish K. Krishnamurthy; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2021)

An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. - Raghavan Kumar; Vikram B. Suresh; Mark A. Anders 001; Steven K. Hsu; Amit Agarwal 001; Vivek K. De; Sanu K. Mathew (ISSCC, 2022)

Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC. - Vikram B. Suresh; Chandra S. Katta; Srinivasan Rajagopalan; Tao Z. Zhou; Amit Kumar Patel; Raju Rakha; Nikhil Krishna Gopalakrishna; Sanu Mathew; Ajat Hukkoo (ISSCC, 2022)

A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. - Raghavan Kumar; Vikram B. Suresh; Sachin Taneja; Mark A. Anders 001; Steven Hsu; Amit Agarwal 001; Vivek De; Sanu Mathew (VLSI Technology and Circuits, 2022)

Guarding Machine Learning Hardware Against Physical Side-channel Attacks. - Anuj Dubey; Rosario Cammarota; Vikram B. Suresh; Aydin Aysu (ACM J. Emerg. Technol. Comput. Syst., 2022)

218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. - Sachin Taneja; Vikram B. Suresh; Raghavan Kumar; Vivek De; Sanu Mathew (VLSI Technology and Circuits, 2023)

A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. - Raghavan Kumar; Vikram B. Suresh; Sachin Taneja; Mark A. Anders 001; Steven Hsu; Amit Agarwal 001; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2023)

A 2455μm2 1.7Gbps Side-Channel Attack-Resistant Masked HMAC-SHA256 Accelerator in Intel 4 CMOS. - Sachin Taneja; Vikram B. Suresh; Raghavan Kumar; Vivek De; Sanu Mathew (CICC, 2025)