Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle. - Tahiyah Nou Shene; Vikramkumar Pudi; K. Sridharan 001; Vineetha Thomas; J. Arthi (IET Comput. Vis., 2015)

A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata. - Vikramkumar Pudi; K. Sridharan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices. - Vikramkumar Pudi; Anupam Chattopadhyay; Thambipillai Srikanthan (ISIC, 2016)

FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. - Anupam Chattopadhyay; Vikramkumar Pudi; Anubhab Baksi; Thambipillai Srikanthan (ISVLSI, 2016)

SHA-3 implementation using ReRAM based in-memory computing architecture. - Debjyoti Bhattacharjee; Vikramkumar Pudi; Anupam Chattopadhyay (ISQED, 2017)

Approximate compressed sensing for hardware-efficient image compression. - Sai Praveen Kadiyala; Vikram Kumar Pudi; Siew-Kei Lam (SoCC, 2017)

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. - Vikramkumar Pudi; K. Sridharan 001; Fabrizio Lombardi (IEEE Trans. Computers, 2017)

CoLPUF : A Novel Configurable LFSR-based PUF. - B. Srinivasu; Vikramkumar Pudi; Anupam Chattopadhyay; Kwok-Yan Lam (APCCAS, 2018)

Efficient and Lightweight Quantized Compressive Sensing using μ-Law. - Vikramkumar Pudi; Anupam Chattopadhyay; Kwok-Yan Lam (ISCAS, 2018)

Lightweight ASIC Implementation of AEGIS-128. - Anubhab Baksi; Vikramkumar Pudi; Swagata Mandal; Anupam Chattopadhyay (ISVLSI, 2018)

An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning. - Ritu Ranjan Shrivastwa; Vikramkumar Pudi; Anupam Chattopadhyay (ISVLSI, 2018)

Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. - Ming Ming Wong; Vikramkumar Pudi; Anupam Chattopadhyay (VLSI-SoC, 2018)

Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study. - Vishal Dey; Vikramkumar Pudi; Anupam Chattopadhyay; Yuval Elovici (VLSID, 2018)

Secure and Lightweight Compressive Sensing Using Stream Cipher. - Vikramkumar Pudi; Anupam Chattopadhyay; Kwok-Yan Lam (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. - Jawad Haj-Yahya; Ming Ming Wong; Vikramkumar Pudi; Shivam Bhasin; Anupam Chattopadhyay (ISQED, 2019)

Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images. - Sai Praveen Kadiyala; Vikram Kumar Pudi; Mohit Garg; Hau T. Ngo; Siew-Kei Lam; Thambipillai Srikanthan (SoCC, 2019)

New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata. - Tingting Zhang; Vikramkumar Pudi; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management. - Vikramkumar Pudi; Srinivasu Bodapati; Sachin Kumar; Anupam Chattopadhyay (iSES, 2020)

A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning. - Ritu Ranjan Shrivastwa; Vikramkumar Pudi; Duo Chen; Rosa Q. So; Anupam Chattopadhyay; Cuntai Guan (IEEE Consumer Electron. Mag., 2020)

Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs. - K. B. Dheeraj Kumar; K. Lakshmi BhanuPrakash Reddy; Vikramkumar Pudi; Srinivasu Bodapati (iSES, 2021)

Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. - K. Lakshmi BhanuPrakash Reddy; K. B. Dheeraj Kumar; Vikramkumar Pudi (VDAT, 2021)

Hardware Implementation of SpoC-128. - Ambati Sathvik; Tirunagari Rahul; Anubhab Baksi; Vikramkumar Pudi (IACR Cryptol. ePrint Arch., 2022)

Inner Product Computation In-Memory Using Distributed Arithmetic. - Vijaya Lakshmi; Vikramkumar Pudi; John Reuben (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. - Vijaya Lakshmi; John Reuben; Vikramkumar Pudi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs. - Lakshmi Sarvaani P; Subba Ramkumar Reddy Annapalli; Vikramkumar Pudi (APCCAS, 2023)

A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips. - Lakshmi Sarvaani P; Subba Ramkumar Reddy Annapalli; Vikramkumar Pudi; Naga Teja Babu M (ISCAS, 2023)

Design of Low Power ALU for RISC-VISA. - Keerthija Puli; Vikramkumar Pudi (iSES, 2023)

Design of Energy Efficient and Low Delay Posit Multiplier. - K. Lakshmi BhanuPrakash Reddy; Haripriya R. S; Keerthija Puli; Subba Ramkumar Reddy Annapalli; Vikramkumar Pudi (VLSID, 2023)

Design of Novel Systolic Array based NTT for CRYSTALS-Kyber scheme. - Keerthija Puli; Vikramkumar Pudi (APCCAS, 2024)

Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics. - Lakshmi Sarvaani P; Subba Ramkumar Reddy Annapalli; Vikramkumar Pudi (ISCAS, 2024)

Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing. - K. Lakshmi BhanuPrakash Reddy; Vikramkumar Pudi; Balasubramanyam Appina; Anupam Chattopadhyay (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. - Lakshmi Bhanuprakash Reddy Konduru; Vikramkumar Pudi; Balasubramanyam Appina (IEEE Trans. Very Large Scale Integr. Syst., 2025)

In-Memory Implementation of an Approximate Adder With Reduced Latency and Error. - Vijaya Lakshmi; Vikramkumar Pudi; John Reuben (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Applying Differential Privacy for Real-Time Monitoring Systems via Compressive Sensing. - Vikramkumar Pudi; Lakshmi Bhanuprakash Reddy Konduru; Balasubramanyam Appina; Anupam Chattopadhyay (IEEE Trans. Consumer Electron., 2025)