Memory optimization for packet classification algorithms. - Juraj Blaho; Jan Korenek; Viktor Pus (ANCS, 2009)

Fast and scalable packet classification using perfect hash functions. - Viktor Pus; Jan Korenek (FPGA, 2009)

Memory optimizations for packet classification algorithms in FPGA. - Viktor Pus; Juraj Blaho; Jan Korenek (DDECS, 2010)

Netbench: Framework for Evaluation of Packet Processing Algorithms. - Viktor Pus; Jiri Tobola; Vlastimil Kosar; Jan Kastil; Jan Korenek (ANCS, 2011)

Hardware architecture for packet classification with prefix coloring. - Viktor Pus; Michal Kajan; Jan Korenek (DDECS, 2011)

Hardware Acceleration for Measurements in 100 Gb/s Networks. - Viktor Pus (AIMS, 2012)

Low-latency modular packet header parser for FPGA. - Viktor Pus; Lukas Kekely; Jan Korenek (ANCS, 2012)

Reducing memory in high-speed packet classification. - Viktor Pus; Jan Korenek (IWCMC, 2012)

Algoritmy klasifikace paketů ; Packet Classification Algorithms. - Viktor Pus (2012)

Design methodology of configurable high performance packet parser for FPGA. - Viktor Pus; Lukas Kekely; Jan Korenek (DDECS, 2014)

CRC based hashing in FPGA using DSP blocks. - Tomás Závodník; Lukas Kekely; Viktor Pus (DDECS, 2014)

Architecture of Effective High-Speed Network Stream Merger. - Pavel Benácek; Hana Kubátová; Viktor Pus (DSD, 2014)

Application specific processor with high level synthesized instructions (abstract only). - Viktor Pus; Pavel Benácek (FPGA, 2014)

Using DSP blocks to compute CRC hash in FPGA (abstract only). - Viktor Pus; Lukas Kekely; Tomás Závodník (FPGA, 2014)

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. - Lukas Kekely; Viktor Pus; Pavel Benácek; Jan Korenek (FPL, 2014)

Software Defined Monitoring of application protocols. - Lukas Kekely; Viktor Pus; Jan Korenek (INFOCOM, 2014)

Hardware accelerated flow measurement of 100 Gb ethernet. - Viktor Pus; Petr Velan; Lukas Kekely; Jan Korenek; Pavel Minarík (IM, 2015)

High-density network flow monitoring. - Petr Velan; Viktor Pus (IM, 2015)

Building a feedback loop to capture evidence of network incidents. - Zdenek Rosa; Tomás Cejka; Martin Zádník; Viktor Pus (CNSM, 2016)

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. - Pavel Benácek; Viktor Pus; Hana Kubátová (FCCM, 2016)

High-speed regular expression matching with pipelined automata. - Denis Matousek; Jan Korenek; Viktor Pus (FPT, 2016)

Software Defined Monitoring of Application Protocols. - Lukas Kekely; Jan Kucera 004; Viktor Pus; Jan Korenek; Athanasios V. Vasilakos (IEEE Trans. Computers, 2016)

Line rate programmable packet processing in 100Gb networks. - Pavel Benácek; Viktor Pus; Jan Korenek; Michal Kekely (FPL, 2017)

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. - Jakub Cabal; Pavel Benácek; Lukas Kekely; Michal Kekely; Viktor Pus; Jan Korenek (FPGA, 2018)

Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. - Lukás Kekely; Martin Spinler; Stepán Friedl; Jiri Sikora; Jan Korenek; Viktor Pus (FPT, 2018)

Verification of Generated RTL from P4 Source Code. - Radek Isa; Pavel Benácek; Viktor Pus (ICNP, 2018)

P4-To-VHDL: Automatic generation of high-speed input and output network blocks. - Pavel Benácek; Viktor Pus; Hana Kubátová; Tomás Cejka (Microprocess. Microsystems, 2018)

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. - Lukás Kekely; Jakub Cabal; Viktor Pus; Jan Korenek (DSD, 2020)