High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. - Panu Sjovall; Vili Viitamäki; Jarno Vanne; Timo D. Hämäläinen (ICASSP, 2017)

High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA. - Vili Viitamäki; Panu Sjovall; Jarno Vanne; Timo D. Hämäläinen (ISCAS, 2017)

Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server. - Panu Sjovall; Vili Viitamäki; Arto Oinonen; Jarno Vanne; Timo D. Hämäläinen; Ari Kulmala (SiPS, 2017)

FPGA-Powered 4K120p HEVC Intra Encoder. - Panu Sjövall; Vili Viitamäki; Jarno Vanne; Timo D. Hämäläinen; Ari Kulmala (ISCAS, 2018)

Live Demonstration: 4K100p HEVC Intra Encoder. - Vili Viitamäki; Panu Sjövall; Jarno Vanne; Timo D. Hämäläinen; Ari Kulmala (ISCAS, 2018)

Feasibility of FPGA accelerated IPsec on cloud. - Markku Vajaranta; Arto Oinonen; Timo D. Hämäläinen; Vili Viitamäki; Jouni Markunmäki; Ari Kulmala (Microprocess. Microsystems, 2019)