FPGA Based High Performance Double-Precision Matrix Multiplication. - Vinay B. Y. Kumar; Siddharth Joshi 005; Sachin B. Patkar; H. Narayanan (Int. J. Parallel Program., 2010)

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields. - Prateek Saxena; Vinay B. Y. Kumar; Dilawar Singh; H. Narayanan; Sachin B. Patkar (PECCS, 2013)

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. - Vinay B. Y. Kumar; Shovan Maity; Sachin B. Patkar (ICCD, 2014)

FPGA-based implementation of M4RM for matrix multiplication over GF(2). - Vivek Kumar; Vinay B. Y. Kumar; Sachin B. Patkar (VDAT, 2014)

Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems. - Janak Porwal; Sanket Diwale; Vinay B. Y. Kumar; Sachin B. Patkar (VLSI-DAT, 2014)

Parallel two step random walk algorithm to analyze VLSI power grid networks. - Satyabrata Dash; Vivek Bangera; Vinay B. Y. Kumar; Gaurav Trivedi; Sachin B. Patkar (VDAT, 2015)

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies. - Vinay B. Y. Kumar; Pinalkumar Engineer; Mandar Datar 001; Yatish Turakhia; Saurabh Agarwal; Sanket Diwale; Sachin B. Patkar (CoRR, 2015)

Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. - Vinay B. Y. Kumar; Kulshreshth Dhiman; Mandar Datar 001; Akash Pacharne; H. Narayanan; Sachin B. Patkar (VLSID, 2016)

Lightweight Forth Programmable NoCs. - Vinay B. Y. Kumar; Deval Shah; Mandar Datar 001; Sachin B. Patkar (VLSID, 2018)

Recruiting Fault Tolerance Techniques for Microprocessor Security. - Vinay B. Y. Kumar; Suman Deb; Rupesh Kumar; Mustafa Khairallah; Anupam Chattopadhyay; Avi Mendelson (ATS, 2019)

ITUS: A Secure RISC-V System-on-Chip. - Vinay B. Y. Kumar; Anupam Chattopadhyay; Jawad Haj-Yahya; Avi Mendelson (SoCC, 2019)

Post-Quantum Secure Boot. - Vinay B. Y. Kumar; Naina Gupta 001; Anupam Chattopadhyay; Michael Kasper; Christoph Krauß; Ruben Niederhagen (DATE, 2020)

Secure Your SoC: Building System-an-Chip Designs for Security. - Shivam Bhasin; Trevor E. Carlson; Anupam Chattopadhyay; Vinay B. Y. Kumar; Avi Mendelson; Romain Poussier; Yaswanth Tavva (SoCC, 2020)

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version). - Anubhab Baksi; Shivam Bhasin; Jakub Breier; Anupam Chattopadhyay; Vinay B. Y. Kumar (IACR Cryptol. ePrint Arch., 2020)

A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis. - Anubhab Baksi; Vinay B. Y. Kumar; Banashri Karmakar; Shivam Bhasin; Dhiman Saha; Anupam Chattopadhyay (IACR Cryptol. ePrint Arch., 2020)

Towards Designing a Secure RISC-V System-on-Chip: ITUS. - Vinay B. Y. Kumar; Suman Deb; Naina Gupta 001; Shivam Bhasin; Jawad Haj-Yahya; Anupam Chattopadhyay; Avi Mendelson (J. Hardw. Syst. Secur., 2020)

Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks. - Anubhab Baksi; Shivam Bhasin; Jakub Breier; Anupam Chattopadhyay; Vinay B. Y. Kumar (DATE, 2021)

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. - Simei Yang; Debjyoti Bhattacharjee; Vinay B. Y. Kumar; Saikat Chatterjee; Sayandip De; Peter Debacker; Diederik Verkest; Arindam Mallik; Francky Catthoor (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)