0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. - Balaji Srinivasan; Vinay Bhaskar Chandratre; Menka Tewani (VLSI Design, 2008)

An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. - Balaji Srinivasan; Vinay Bhaskar Chandratre (VLSI Design, 2010)

500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". - Menka Sukhwani; Vinay Bhaskar Chandratre; Megha Thomas; C. K. Pithawa; Vangmayee Sharda (ISVLSI, 2011)

Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. - Shiv Kumar; Vinay Bhaskar Chandratre; Sudheer K. Mohammed; C. K. Pithawa (VLSI Design, 2011)