Cyclic stress tests for full scan circuits. - Vinay Dabholkar; Sreejit Chakravarty; J. Najm; Janak H. Patel (VTS, 1995)

Computing stress tests for interconnect defects. - Vinay Dabholkar; Sreejit Chakravarty (Asian Test Symposium, 1997)

Computing Stress Tests for Gate Oxide Shorts. - Vinay Dabholkar; Sreejit Chakravarty (VLSI Design, 1998)

Techniques for minimizing power dissipation in scan and combinational circuits during test application. - Vinay Dabholkar; Sreejit Chakravarty; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)