High Performance and Energy Efficient AMD and BWAD Pooling Schemes Characterised for CNN Accelerators. - Vinay Rayapati; Mahati Basavaraju; Madhav Rao (DSD, 2023)

POCO: Hardware Characterization of Activation Functions using POSIT-CORDIC Architecture. - Mahati Basavaraju; Vinay Rayapati; Madhav Rao (ISCAS, 2024)

VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory Vector Co-Processor. - Chithambara Moorthii J; Vinay Rayapati; Nanditha Rao; Manan Suri (ISCAS, 2024)

FPGA-based Hardware Software Co-design to Accelerate Brain Tumour Segmentation. - Vinay Rayapati; Gogireddy Ravi Kiran Reddy; Gandi Ajay Kumar; Saketh Gajawada; Sanampudi Gopala Krishna Reddy; Nanditha Rao (ISCAS, 2024)

Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats. - Mahati Basavaraju; Vinay Rayapati; Madhav Rao (ISQED, 2024)

Clustering-Based-Approach for Hardware Implementation of Activation Functions. - Mahati Basavaraju; Omkar Girish Ratnaparkhi; Vinay Rayapati; Madhav Rao (SOCC, 2024)

EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture. - Vinay Rayapati; Sanampudi Gopala Krishna Reddy; Gandi Ajay Kumar; Gogireddy Ravi Kiran Reddy; Madhav Rao (VLSID, 2024)

Layer-Specific Hardware Pooling Designs for CNN Accelerators. - Vinay Rayapati; Mahati Basavaraju; Madhav Rao (VLSID, 2025)