Out of order floating point coprocessor for RISC V ISA. - Vinayak Patil; Aneesh Raveendran; P. M. Sobha; A. David Selvakumar; Vivian Desalphine (VDAT, 2015)

RISC-V out-of-order data conversion co-processor. - Aneesh Raveendran; Vinayak Patil; Vivian Desalphine; P. M. Sobha; A. David Selvakumar (VDAT, 2015)

Throughput Improvement in Hybrid MIMO Cognitive Radio Using Simultaneous Narrowband and Wideband System. - Vinayak Patil; Chetna Singhal 001 (COMSNETS, 2019)

HCR-WSN: Hybrid MIMO cognitive radio system for wireless sensor network. - Chetna Singhal 001; Vinayak Patil (Comput. Commun., 2021)