A voltage reduction technique for battery-operated systems. - Vincent von Kaenel; Peter Macken; Marc G. R. Degrauwe (IEEE J. Solid State Circuits, 1990)

Logic design for low-voltage/low-power CMOS circuits. - Christian Piguet; Jean-Marc Masgonty; Vincent von Kaenel; Thierry Schneider (ISLPD, 1995)

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation. - Vincent von Kaenel; Daniel Aebischer; Christian Piguet; Evert Dijkstra (IEEE J. Solid State Circuits, 1996)

A 2.1-MHz crystal oscillator time base with a current consumption under 500 nA. - Daniel Aebischer; Henri J. Oguey; Vincent von Kaenel (IEEE J. Solid State Circuits, 1997)

A 2× load/store pipe for a low-power 1-GHz embedded processor. - Zongjian Chen; Daniel Murray; Steve Nishimoto; Mark H. Pearce; Max Oyker; Daniel Rodriguez; Robert Rogenmoser; Dongwook (Drew) Suh; Erik Supnet; Vincent von Kaenel; George Yiu (IEEE J. Solid State Circuits, 2003)

Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. - Brian Campbell 004; James Burnette; Naveen Javarappa; Vincent von Kaenel (CICC, 2007)

Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC. - Vincent von Kaenel; Toshinari Takayanagi (CICC, 2007)

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. - Zongjian Chen; Priya Ananthanarayanan; Sukalp Biswas; Brian Campbell 004; Hao Chen; Shaishav Desai; Dominic Go; Rajat Goel; Vincent von Kaenel; Jason Kassoff; Fabian Klass; Weichun Ku; et al. (ISSCC, 2007)