Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization. - Mark Po-Hung Lin; Yi-Ting He; Vincent Wei-Hao Hsiao; Rong-Guey Chang; Shuenn-Yuh Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC. - Mark Po-Hung Lin; Vincent Wei-Hao Hsiao; Chun-Yu Lin (DAC, 2014)

Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing. - Mark Po-Hung Lin; Vincent Wei-Hao Hsiao; Chun-Yu Lin; Nai-Chen Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)