Achieving full functional coverage for the forwarding unit of pipelined processors. - V. S. Vineesh; Nihar Hage; B. Karthik; Virendra Singh (EWDTS, 2017)

Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. - Vineesh V. S.; Binod Kumar 001; Rushikesh Shinde; Akshay Jaiswal; Harsh Bhargava; Virendra Singh (ATS, 2019)

Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. - V. S. Vineesh; Binod Kumar 001; Jay Adhaduk (VDAT, 2019)

LUT-based Circuit Approximation with Targeted Error Guarantees. - Vinod G. U; Vineesh V. S.; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (ATS, 2020)

Analyzing Hardware Security Properties of Processors through Model Checking. - Binod Kumar 001; Akshay Kumar Jaiswal; V. S. Vineesh; Rushikesh Shinde (VLSID, 2020)

Enhancing Testbench Quality via Genetic Algorithm. - Harsh Bhargav; Vineesh V. S.; Binod Kumar 001; Virendra Singh (MWSCAS, 2021)

Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. - V. S. Vineesh; Binod Kumar 001; Rushikesh Shinde; Neelam Sharma; Masahiro Fujita; Virendra Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. - Binod Kumar 001; V. S. Vineesh; Puneet Nemade; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)