An efficient combinationality check technique for the synthesis of cyclic combinational circuits. - Vineet Agarwal; Navneeth Kankani; Ravishankar Rao; Sarvesh Bhardwaj; Janet Meiling Wang (ASP-DAC, 2005)

Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). - Vineet Agarwal; Janet Meiling Wang (ASP-DAC, 2006)

A probabilistic analysis of pipelined global interconnect under process variations. - Navneeth Kankani; Vineet Agarwal; Janet Meiling Wang (ASP-DAC, 2006)

Delay Uncertainty Reduction by Interconnect and Gate Splitting. - Vineet Agarwal; Jin Sun 006; Alexander V. Mitev; Janet Meiling Wang (ASP-DAC, 2007)

Delay Uncertainty Reduction by Gate Splitting. - Vineet Agarwal; Jin Sun 006; Janet Meiling Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Detection and prevention of botnets and malware in an enterprise network. - Manoj Rameshchandra Thakur; Divye Raj Khilnani; Kushagra Gupta; Sandeep Jain; Vineet Agarwal; Suneeta Sane; Sugata Sanyal; Prabhakar S. Dhekne (Int. J. Wirel. Mob. Comput., 2012)

Automatic Hierarchical Arrangement of Vector Designs. - Matthew Fisher; Vineet Agarwal; Tarun Beri (Eurographics (Short Papers), 2021)

Building a best-in-class automated de-identification tool for electronic health records through ensemble learning. - Karthik Murugadoss; Ajit Rajasekharan; Bradley A. Malin; Vineet Agarwal; Sairam Bade; Jeff R. Anderson; Jason L. Ross; William A. Faubion Jr.; John D. Halamka; Venky Soundararajan; Sankar Ardhanari (Patterns, 2021)