An External Test Approach for Network-on-a-Chip Switches. - Jaan Raik; Vineeth Govind; Raimund Ubar (ATS, 2006)

Test Configurations for Diagnosing Faulty Links in NoC Switches. - Jaan Raik; Raimund Ubar; Vineeth Govind (ETS, 2007)

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. - Jaan Raik; Vineeth Govind; Raimund Ubar (IET Comput. Digit. Tech., 2009)

Low-area boundary BIST architecture for mesh-like network-on-chip. - Jaan Raik; Vineeth Govind (DDECS, 2012)

Ultra-low latency NoC testing via pseudo-random test pattern compaction. - Hervé Tatenguem; Alessandro Strano; Vineeth Govind; Jaan Raik; Davide Bertozzi (ISSoC, 2012)

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. - Pietro Saltarelli; Behrad Niazmand; Jaan Raik; Vineeth Govind; Thomas Hollstein; Gert Jervan; Ranganathan Hariharan (NOCS, 2015)