SCOC IP Cores for Custom Built Supercomputing Nodes. - Nagarajan Venkateswaran; Rajagopal Hariharan; Vinesh Srinivasan; Ram Srivatsa Kannan; Prashanth Thinakaran; Vigneshwaran Sankaran; Bharanidharan Vasudevan; Ravindhiran Mukundrajan; Nachiappan Chidambaram Nachiappan; Aswin Sridharan; Karthikeyan P. Saravanan; Vignesh Adhinarayanan; et al. (ISVLSI, 2012)

Compilation Accelerator on Silicon. - Nagarajan Venkateswaran; Vinesh Srinivasan; Ram Srivatsa Kannan; Prashanth Thinakaran; Rajagopal Hariharan; Bharanidharan Vasudevan; Nachiappan Chidambaram Nachiappan; Karthikeyan P. Saravanan; Aswin Sridharan; Vigneshwaran Sankaran; Vignesh Adhinarayanan; V. S. Vignesh; et al. (ISVLSI, 2012)

Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores. - Nagarajan Venkateswaran; Kartik Lakshminarasimhan; Akash Sridhar; Prashanth Thinakaran; Rajagopal Hariharan; Vinesh Srinivasan; Ram Srivatsa Kannan; Aswin Sridharan (ISVLSI, 2013)

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. - Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Brandon H. Dwiel; Rangeen Basu Roy Chowdhury; Vinesh Srinivasan; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (Hot Chips Symposium, 2015)

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. - Vinesh Srinivasan; Rangeen Basu Roy Chowdhury; Elliott Forbes; Randy Widialaksono; Zhenqian Zhang; Joshua Schabel; Sungkwan Ku; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (ICCD, 2017)

Slipstream Processors Revisited: Exploiting Branch Sets. - Vinesh Srinivasan; Rangeen Basu Roy Chowdhury; Eric Rotenberg (ISCA, 2020)