Place-and-Route Impact on the Security of DPL Designs in FPGAs. - Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Laurent Sauvage; Philippe Hoogvorst; Maxime Nassar; Tarik Graba; Vinh-Nga Vong (HOST, 2008)

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. - Sylvain Guilley; Laurent Sauvage; Florent Flament; Vinh-Nga Vong; Philippe Hoogvorst; Renaud Pacalet (IEEE Trans. Computers, 2010)