SwitchCraft: a framework for transistor network design. - Vinicius Callegaro; Felipe de Souza Marques; Carlos Eduardo Klock; Leomar Soares da Rosa Jr.; Renato P. Ribas; André Inácio Reis (SBCCI, 2010)

Efficient method to compute minimum decision chains of Boolean functions. - Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2011)

Area impact analysis of via-configurable regular fabric for digital integrated circuit design. - Vinícius Dal Bem; Paulo F. Butzen; Carlos Eduardo Klock; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2011)

Contributions to the evaluation of ensembles of combinational logic gates. - Renato P. Ribas; Simone Bavaresco; N. Schuch; Vinicius Callegaro; Marcelo Lubaszewski; André Inácio Reis (Microelectron. J., 2011)

KL-cut based digital circuit remapping. - Lucas Machado; Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (NORCHIP, 2012)

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

Efficient transistor-level design of CMOS gates. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (ACM Great Lakes Symposium on VLSI, 2013)

Iterative remapping respecting timing constraints. - Lucas Machado; Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (ISVLSI, 2013)

Transistor-level optimization of CMOS complex gates. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (LASCAS, 2013)

Read-polarity-once Boolean functions. - Vinicius Callegaro; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Improving the methodology to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (SBCCI, 2013)

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. - Vinicius Callegaro; Felipe S. Marranghello; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ICCD, 2015)

SOP based logic synthesis for memristive IMPLY stateful logic. - Felipe S. Marranghello; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (ICCD, 2015)

Improved logic synthesis for memristive stateful logic using multi-memristor implication. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (ISCAS, 2015)

Factored Forms for Memristive Material Implication Stateful Logic. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Graph-Based Transistor Network Generation Method for Supergate Design. - Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Simple and Effective Heuristic Method for Threshold Logic Identification. - Augusto Neutzling; Mayler G. A. Martins; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Four-Level Forms for Memristive Material Implication Logic. - Felipe S. Marranghello; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (IEEE Trans. Very Large Scale Integr. Syst., 2019)