Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (J. Low Power Electron., 2010)

Transistor network restructuring against NBTI degradation. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2010)

Transistor Sizing Analysis of Regular Fabrics. - Felipe S. Marranghello; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas; Francesc Moll (ARCS Workshops, 2011)

Impact and optimization of lithography-aware regular layout in digital circuit design. - Vinícius Dal Bem; Paulo F. Butzen; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ICCD, 2011)

Area impact analysis of via-configurable regular fabric for digital integrated circuit design. - Vinícius Dal Bem; Paulo F. Butzen; Carlos Eduardo Klock; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2011)

Transistor sizing in lithography-aware regular fabrics. - Felipe S. Marranghello; Vinícius Dal Bem; André Inácio Reis; Francesc Moll; Renato P. Ribas (SBCCI, 2011)

Lithography analysis of via-configurable transistor-array fabrics. - Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (NORCHIP, 2012)

Design of CMOS logic gates with enhanced robustness against aging degradation. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2012)

Logic synthesis for manufacturability considering regularity and lithography printability. - Lucas Machado; Vinícius Dal Bem; Francesc Moll; Sergio Gómez; Renato P. Ribas; André Inácio Reis (ISVLSI, 2013)

Analytical logical effort formulation for minimum active area under delay constraints. - Caio G. P. Alegretti; Vinícius Dal Bem; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

BTI and HCI first-order aging estimation for early use in standard cell technology mapping. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2013)

SAT based environment for logical capacity evaluation of via configurable block templates. - Vinícius Dal Bem (2016)

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. - Vinícius Dal Bem; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (IEEE Trans. Emerg. Top. Comput., 2017)