NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

Efficient transistor-level design of CMOS gates. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (ACM Great Lakes Symposium on VLSI, 2013)

Transistor-level optimization of CMOS complex gates. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (LASCAS, 2013)

Improving the methodology to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (SBCCI, 2013)

Exploring Independent Gates in FinFET-Based Transistor Network Generation. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar Soares da Rosa Jr. (SBCCI, 2014)

Performance evaluation of optimized transistor networks built using independent-gate FinFET. - Andres M. A. Valdes; Vinicius N. Possani; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (LASCAS, 2016)

Graph-Based Transistor Network Generation Method for Supergate Design. - Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Binary adder circuit design using emerging MIGFET devices. - Jeferson José Baqueta; Felipe S. Marranghello; Vinicius N. Possani; Augusto Neutzling; André Inácio Reis; Renato P. Ribas (ISQED, 2017)

Transistor Count Optimization in IG FinFET Network Design. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Unlocking fine-grain parallelism for AIG rewriting. - Vinicius N. Possani; Yi-Shan Lu; Alan Mishchenko; Keshav Pingali; Renato P. Ribas; André Inácio Reis (ICCAD, 2018)

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; André Inácio Reis; Renato P. Ribas (SBCCI, 2018)

SAT-Sweeping Enhanced for Logic Synthesis. - Luca G. Amarù; Felipe S. Marranghello; Eleonora Testa; Christopher Casares; Vinicius N. Possani; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2020)

Exact Benchmark Circuits for Logic Synthesis. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; Pierre-Emmanuel Gaillardon; André Inácio Reis; Renato Perez Ribas (IEEE Des. Test, 2020)

Parallel Combinational Equivalence Checking. - Vinicius N. Possani; Alan Mishchenko; Renato P. Ribas; André Inácio Reis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

LUT-Based Optimization For ASIC Design Flow. - Luca Gaetano Amarù; Vinicius N. Possani; Eleonora Testa; Felipe S. Marranghello; Christopher Casares; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2021)

Majority-based Design Flow for AQFP Superconducting Family. - Giulia Meuli; Vinicius N. Possani; Rajinder Singh; Siang-Yun Lee; Alessandro Tempia Calvino; Dewmini Sudara Marakkalage; Patrick Vuillod; Luca G. Amarù; Scott Chase; Jamil Kawa; Giovanni De Micheli (DATE, 2022)