NBTI-aware technique for transistor sizing of high-performance CMOS gates. - Maurício Banaszeski da Silva; Vinicius V. A. Camargo; Lucas Brusamarello; Gilson I. Wirth; Roberto da Silva (LATW, 2009)

Circuit simulation of workload-dependent RTN and BTI based on trap kinetics. - Vinicius V. A. Camargo; Ben Kaczer; Tibor Grasser; Gilson I. Wirth (Microelectron. Reliab., 2014)

Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits. - Vinicius V. A. Camargo; Ben Kaczer; Gilson I. Wirth; Tibor Grasser; Guido Groeseneken (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Transistor-Level Radiation Hardening by Design Techniques in Complex Gates. - Bruno T. Ferraz; Henrique Kessler; Vinicius V. A. Camargo (J. Circuits Syst. Comput., 2022)