A 64-b microprocessor with multimedia support. - Lavi Lev; Andy Charnas; Marc Tremblay; Alexander Dalal; Bruce A. Frederick; Chakra R. Srivatsa; David Greenhill; Dennis L. Wendell; Duy Dinh Pham; Eric Anderson; Hemraj K. Hingarh; Inayat Razzack; et al. (IEEE J. Solid State Circuits, 1995)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino (IEEE J. Solid State Circuits, 1998)