Voltage scaling and repeater insertion for high-throughput low-power interconnects. - Vinita V. Deodhar; Jeffrey A. Davis (ISCAS (5), 2003)

Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. - Vinita V. Deodhar; Jeffrey A. Davis (ISQED, 2005)

Designing for signal integrity in wave-pipelined SOC global interconnects. - Vinita V. Deodhar; Jeffrey A. Davis (SoCC, 2005)

Optimization of throughput performance for low-power VLSI interconnects. - Vinita V. Deodhar; Jeffrey A. Davis (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. - Ajay Joshi; Vinita V. Deodhar; Jeffrey A. Davis (VLSI Design, 2006)

Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects. - Vinita V. Deodhar; Jeffrey A. Davis (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)