Synthesis of Analog CMOS Circuits. - K. Ravi Shanker; Vinita Vasudevan (VLSI Design, 1997)

A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits. - Prakash Gopalakrishnan; Vinita Vasudevan (VLSI Design, 1998)

Symbolic Analysis of Analog Integrated Circuits. - C. F. Prince; Vinita Vasudevan (VLSI Design, 1998)

A Transistor Level Placement Tool for Custom Cell Generation. - Ranjit K. Dash; T. Pramod; Vinita Vasudevan; M. Ramakrishna 001 (VLSI Design, 2000)

Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD. - Rajesh T. N. Rajaram; Vinita Vasudevan (VLSI Design, 2000)

Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique. - Vinita Vasudevan; M. Ramakrishna 001 (DAC, 2003)

A time-domain technique for computation of noise spectral density in switched capacitor circuits. - Vinita Vasudevan (ISCAS (1), 2003)

An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC. - Sunil Rafeeque; Vinita Vasudevan (ISCAS (1), 2004)

A Built-in-Self-Test Scheme for Digital to Analog Converters. - Sunil Rafeeque; Vinita Vasudevan (VLSI Design, 2004)

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. - Sunil Rafeeque; Vinita Vasudevan (J. Electron. Test., 2004)

A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits. - Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory. - Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits. - Vinita Vasudevan; M. Ramakrishna 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. - Vinita Vasudevan (DAC, 2005)

Hardware-software co-simulation of bus-based reconfigurable systems. - K. N. Vikram; Vinita Vasudevan (Microprocess. Microsystems, 2005)

A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters. - Sunil Rafeeque; Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Scheduling divisible loads on partially reconfigurable hardware. - K. N. Vikram; Vinita Vasudevan (FCCM, 2006)

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures. - K. N. Vikram; Vinita Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators. - Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

On the computation of criticality in statistical timing analysis. - S. Ramprasath 001; Vinita Vasudevan (ICCAD, 2012)

Statistical Criticality Computation Using the Circuit Delay. - S. Ramprasath 001; Vinita Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

An efficient algorithm for statistical timing yield optimization. - S. Ramprasath 001; Vinita Vasudevan (DAC, 2015)

An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form. - Vinita Vasudevan; M. Ramakrishna 001 (DAC, 2015)

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. - Ramprasath S 001; Vinita Vasudevan (ACM Trans. Design Autom. Electr. Syst., 2016)

A Skew-Normal Canonical Model for Statistical Static Timing Analysis. - Ramprasath S 001; Madiwalar Vijaykumar; Vinita Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices. - Vinita Vasudevan; M. Ramakrishna 001 (CoRR, 2017)

A Hierarchical Technique for Statistical Path Selection and Criticality Computation. - P. R. Chithira; Vinita Vasudevan (ACM Trans. Design Autom. Electr. Syst., 2017)

Optimizing power-accuracy trade-off in approximate adders. - D. Celia; Vinita Vasudevan; Nitin Chandrachoodan (DATE, 2018)

Probabilistic Error Modeling for Two-part Segmented Approximate Adders. - D. Celia; Vinita Vasudevan; Nitin Chandrachoodan (ISCAS, 2018)

Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition. - V. Charumathi; M. Ramakrishna 001; Vinita Vasudevan (CoRR, 2019)

Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization. - Basava Naga Girish Koneru; Vinita Vasudevan (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework. - P. R. Chithira; Vinita Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders. - Celia Dharmaraj; Vinita Vasudevan; Nitin Chandrachoodan (IET Comput. Digit. Tech., 2021)

A Smoothed LASSO-Based DNN Sparsification Technique. - Basava Naga Girish Koneru; Nitin Chandrachoodan; Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders. - Celia Dharmaraj; Vinita Vasudevan; Nitin Chandrachoodan (ACM Trans. Embed. Comput. Syst., 2021)

IBIA: Bayesian Inference via Incremental Build-Infer-Approximate operations on Clique Trees. - Shivani Bathla; Vinita Vasudevan (CoRR, 2022)

MPE inference using an Incremental Build-Infer-Approximate Paradigm. - Shivani Bathla; Vinita Vasudevan (CoRR, 2022)

Fast and Accurate Proper Orthogonal Decomposition using Efficient Sampling and Iterative Techniques for Singular Value Decomposition. - V. Charumathi; M. Ramakrishna 001; Vinita Vasudevan (ACM Trans. Math. Softw., 2022)

Approximate inference of marginals using the IBIA framework. - Shivani Bathla; Vinita Vasudevan (NeurIPS, 2023)

IBIA: An Incremental Build-Infer-Approximate Framework for Approximate Inference of Partition Function. - Shivani Bathla; Vinita Vasudevan (Trans. Mach. Learn. Res., 2023)

A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference. - Shivani Bathla; Vinita Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Exact Computation of Error in Approximate Circuits using SAT and Message-Passing Algorithms. - S. Ramprasath 001; Marrivada Gopala Krishna Sai Charan; Vinita Vasudevan (CoRR, 2024)