Application of Formal Methods for System-Level Verification of Network on Chip. - Vinitha Arakkonam Palaniveloo; Arcot Sowmya (ISVLSI, 2011)

Formal Estimation of Worst-Case Communication Latency in a Network-on-Chip. - Vinitha Arakkonam Palaniveloo; Arcot Sowmya (ISVLSI, 2012)

Improving GA-Based NoC Mapping Algorithms Using a Formal Model. - Vinitha Arakkonam Palaniveloo; Jude Angelo Ambrose; Arcot Sowmya (ISVLSI, 2014)

System level modeling and verification of NoC components using model checking. - Vinitha Arakkonam Palaniveloo (2014)