Resolution-Oriented Fault Interrelationships in Combinational Logic Networks. - Vinod K. Agarwal; Gerald M. Masson (IEEE Trans. Computers, 1977)

Recursive Coverage Projection of Test Sets. - Vinod K. Agarwal; Gerald M. Masson (IEEE Trans. Computers, 1979)

A Functional Form Approach to Test Set Coverage in Tree Networks. - Vinod K. Agarwal; Gerald M. Masson (IEEE Trans. Computers, 1979)

A microprocessor based tea dryer controller. - S. S. S. P. Rao; Vinod K. Agarwal (SIGSMALL, 1980)

Multiple Fault Detection in Programmable Logic Arrays. - Vinod K. Agarwal (IEEE Trans. Computers, 1980)

Generic Fault Characterizations for Table Look-Up Coverage Bounding. - Vinod K. Agarwal; Gerald M. Masson (IEEE Trans. Computers, 1980)

Multiple Fault Testing of Large Circuits by Single Fault Test Sets. - Vinod K. Agarwal; Andy S. F. Fung (IEEE Trans. Computers, 1981)

Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis. - Michael G. Lamoureux; Vinod K. Agarwal (ITC, 1983)

An Efficient VLSI Dictionary Machine. - Arun K. Somani; Vinod K. Agarwal (ISCA, 1984)

A Design for Machines with Built-In Tolerance to Soft Errors. - Yvon Savaria; Vinod K. Agarwal; Nicholas C. Rumin; Jeremiah F. Hayes (ITC, 1984)

Higher Certainty of Error Coverage by Output Data Modification. - Yervant Zorian; Vinod K. Agarwal (ITC, 1984)

Data Flow Anomaly Detection. - Jacek Jachner; Vinod K. Agarwal (IEEE Trans. Software Eng., 1984)

The McBOOLE logic minimizer. - Michel R. Dagenais; Vinod K. Agarwal; Nicholas C. Rumin (DAC, 1985)

Testing Properties and Applications of Inverter-Free PLA's. - Vinod K. Agarwal; Janusz Rajski (ITC, 1985)

Implementing a Built-In Self-Test PLA Design. - Robert P. Treuer; Hideo Fujiwara; Vinod K. Agarwal (IEEE Des. Test, 1985)

An Efficient Unsorted VLSI Dictionary Machine. - Arun K. Somani; Vinod K. Agarwal (IEEE Trans. Computers, 1985)

Testability Measures : What Do They Do for ATPG ? - André Ivanov; Vinod K. Agarwal (ITC, 1986)

A Theory for the Design of Soft-Error-Tolerant VLSI Circuits. - Yvon Savaria; Jeremiah F. Hayes; Nicholas C. Rumin; Vinod K. Agarwal (IEEE J. Sel. Areas Commun., 1986)

A Fault-Tolerant Modular Architecture for Binary Trees. - A. S. Mahmudul Hassan; Vinod K. Agarwal (IEEE Trans. Computers, 1986)

McBOOLE: A New Procedure for Exact Logic Minimization. - Michel R. Dagenais; Vinod K. Agarwal; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

Testing and Applications of Inverter-Free PLAs. - Janusz Rajski; Vinod K. Agarwal (IEEE Des. Test, 1987)

A Generalized Theory for System Level Diagnosis. - Arun K. Somani; Vinod K. Agarwal; David Avis (IEEE Trans. Computers, 1987)

A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. - Robert P. Treuer; Vinod K. Agarwal; Hideo Fujiwara (IEEE Trans. Computers, 1987)

An iterative technique for calculating aliasing probability of linear feedback signature registers. - André Ivanov; Vinod K. Agarwal (FTCS, 1988)

Aliasing probability of non-exhaustive randomized syndrome tests. - Robert C. Aitken; Vinod K. Agarwal (ICCAD, 1988)

On Multiple Fault Coverage and Aliasing Probability Measures. - Henry Cox; André Ivanov; Vinod K. Agarwal; Janusz Rajski (ITC, 1988)

Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Janusz Rajski (ITC, 1988)

A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures. - Michael C. Howells; Vinod K. Agarwal (IEEE Trans. Computers, 1988)

Dynamic testability measures for ATPG. - André Ivanov; Vinod K. Agarwal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Distributed syndrome decoding for regular interconnected structures. - Arun K. Somani; Vinod K. Agarwal (FTCS, 1989)

A diagnosis method using pseudo-random vectors without intermediate signatures. - Robert C. Aitken; Vinod K. Agarwal (ICCAD, 1989)

Testing of Glue Logic Interconnects Using Boundary Scan Architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Janusz Rajski; Benoit Nadeau-Dostie (ITC, 1989)

: Experiments on Aliasing in Signature Analysis Registers. - Dhiren Xavier; Robert C. Aitken; André Ivanov; Vinod K. Agarwal (ITC, 1989)

t/s-Diagnosable Systems: A Characterization and Diagnosis Algorithm. - Anindya Das; Krishnaiyan Thulasiraman; Vinod K. Agarwal; K. B. Lakshmanan (WG, 1989)

On the Complexity of Single Fault Set Diagnosability and Diagnosis Problems. - Arun K. Somani; Vinod K. Agarwal; David Avis (IEEE Trans. Computers, 1989)

An analysis of the probabilistic behavior of linear feedback signature registers. - André Ivanov; Vinod K. Agarwal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A new procedure for weighted random built-in self-test. - Fidel Muradali; Vinod K. Agarwal; Benoit Nadeau-Dostie (ITC, 1990)

Serial Interfacing for Embedded-Memory Testing. - Benoit Nadeau-Dostie; Allan Silburt; Vinod K. Agarwal (IEEE Des. Test Comput., 1990)

Optimizing error masking in BIST by output data modification. - Yervant Zorian; Vinod K. Agarwal (J. Electron. Test., 1990)

Fast Signature Computation for Linear Compactors. - D. Lambidonis; André Ivanov; Vinod K. Agarwal (ITC, 1991)

Diagnosis of T/S-Diagnosable Systems. - Anindya Das; Krishnaiyan Thulasiraman; Vinod K. Agarwal (J. Circuits Syst. Comput., 1991)

Iterative algorithms for computing aliasing probabilities. - André Ivanov; Corot W. Starke; Vinod K. Agarwal; Wilfried Daehn; Matthias Gruetzner; Tom W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Wafer Testing with Pairwise Comparisons. - Kaiyuan Huang; Vinod K. Agarwal; Laurence E. LaForge (FTCS, 1992)

Performance Evaluation of Latency Tolerant Architectures. - Shashank S. Nemawarkar; Ramaswamy Govindarajan; Guang R. Gao; Vinod K. Agarwal (ICCI, 1992)

A system level synthesis framework for computer architectures. - Oryal Tanir; Vinod K. Agarwal; P. C. P. Bhatt (RSP, 1992)

Distributed Diagnosis Algorithms for Regular Interconnected Structures. - Arun K. Somani; Vinod K. Agarwal (IEEE Trans. Computers, 1992)

BIST of PCB interconnects using boundary-scan architecture. - Abu S. M. Hassan; Vinod K. Agarwal; Benoit Nadeau-Dostie; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Using an asymmetric error model to study aliasing in signature analysis registers. - Dhiren Xavier; Robert C. Aitken; André Ivanov; Vinod K. Agarwal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Computing the probability of undetected error for shortened cyclic codes. - Vinod K. Agarwal; André Ivanov (IEEE Trans. Commun., 1992)

A Novel Methodology Using Genetic Algorithms for the Design of Caches and Cache Replacement Policy. - Erik R. Altman; Vinod K. Agarwal; Guang R. Gao (ICGA, 1993)

Fault Location Algorithms for Repairable Embedded. - Robert P. Treuer; Vinod K. Agarwal (ITC, 1993)

The design of a library support system for a telecommunication system synthesis environment. - Oryal Tanir; Vinod K. Agarwal; P. C. P. Bhatt (RSP, 1993)

Analysis of Multithreaded Multiprocessors with Distributed Shared Memory. - Shashank S. Nemawarkar; Ramaswamy Govindarajan; Guang R. Gao; Vinod K. Agarwal (SPDP, 1993)

Built-In Self-Diagnosis for Repairable Embedded RAMs. - Robert P. Treuer; Vinod K. Agarwal (IEEE Des. Test Comput., 1993)

Distributed Fault diagnosis of a Ring of Processors. - Anindya Das; Krishnaiyan Thulasiraman; K. B. Lakshmanan; Vinod K. Agarwal (Parallel Process. Lett., 1993)

Multiprocessor Fault Diagnosis Under Local Constraints. - Anindya Das; Krishnaiyan Thulasiraman; Vinod K. Agarwal; K. B. Lakshmanan (IEEE Trans. Computers, 1993)

DASE: An Environment for System Level Telecommunication Design Exploration and Modelling. - Oryal Tanir; Vinod K. Agarwal; P. C. P. Bhatt (CAST, 1994)

A Comparative Study of Multiprocessor List Scheduling Heuristics. - Guoning Liao; Erik R. Altman; Vinod K. Agarwal; Guang R. Gao (HICSS (1), 1994)

VAMP: A Hierarchical Framework for Design for Manufacturability. - Morie E. Malowany; Gordon W. Roberts; Vinod K. Agarwal (ISCAS, 1994)

Performance of Interconnection Network in Multithreaded Architectures. - Shashank S. Nemawarkar; Ramaswamy Govindarajan; Guang R. Gao; Vinod K. Agarwal (PARLE, 1994)

Diagnosis of t/(t+1)-Diagnosable Systems. - Anindya Das; Krishnaiyan Thulasiraman; Vinod K. Agarwal (SIAM J. Comput., 1994)

Almost Sure Diagnosis of Almost Every Good Element. - Laurence E. LaForge; Kaiyuan Huang; Vinod K. Agarwal (IEEE Trans. Computers, 1994)

Distributed Probabilistic Diagnosis of MCMs on Large Area. - Koppolu Sasidhar; Abhijit Chatterjee; Vinod K. Agarwal; Joseph L. A. Hughes (ITC, 1995)

A Specification-Driven Architectural Design Environment. - Oryal Tanir; Vinod K. Agarwal; P. C. P. Bhatt (Computer, 1995)

VTS 1994 Panel Report on BIST for Consumer Products. - Vinod K. Agarwal (IEEE Des. Test Comput., 1995)

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes. - D. Lambidonis; Vinod K. Agarwal; André Ivanov; Dhiren Xavier (J. Electron. Test., 1995)

Fast signature computation for BIST linear compactors. - D. Lambidonis; André Ivanov; Vinod K. Agarwal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing. - Kaiyuan Huang; Vinod K. Agarwal; Laurence E. LaForge; Krishnaiyan Thulasiraman (IEEE Trans. Parallel Distributed Syst., 1995)

Embedded Test and Measurement Critical for Deep Submicron Technology. - Vinod K. Agarwal (Asian Test Symposium, 1997)

Correct Diagnosis of Almost All Faulty Units in a Multiprocessor System. - Krishnaiyan Thulasiraman; Anindya Das; Kaiyuan Huang; Vinod K. Agarwal (J. Circuits Syst. Comput., 1998)

Diagnosis of clustered faults and wafer testing. - Kaiyuan Huang; Vinod K. Agarwal; Krishnaiyan Thulasiraman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Invited Talk: Embedded Test for Systems-on-a-Chip. - Vinod K. Agarwal (VLSI Design, 1999)

VTS 1999 Keynote Address Embedded Test OR External Test. - Vinod K. Agarwal (VTS, 1999)