Optimal interpreters for lambda-calculus based functional languages. - Vinod Kathail (1990)

Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. - Michael S. Schlansker; Vinod Kathail (LCPC, 1993)

Height reduction of control recurrences for ILP processors. - Michael S. Schlansker; Vinod Kathail; Sadun Anik (MICRO, 1994)

Critical path reduction for scalar programs. - Michael S. Schlansker; Vinod Kathail (MICRO, 1995)

Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. - Santosh G. Abraham; Vinod Kathail; Brian L. Deitrich (MICRO, 1996)

Parallelization of Control Recurrences for ILP Processors. - Michael S. Schlansker; Vinod Kathail; Sadun Anik (Int. J. Parallel Program., 1996)

Techniques for critical path reduction of scalar programs. - Michael S. Schlansker; Vinod Kathail (Int. J. Parallel Program., 1997)

Meld Scheduling: A Technique for Relaxing Scheduling Constraints. - Santosh G. Abraham; Vinod Kathail; Brian L. Deitrich (Int. J. Parallel Program., 1998)

Automatic Architectural Synthesis of VLIW and EPIC Processors. - Shail Aditya; B. Ramakrishna Rau; Vinod Kathail (ISSS, 1999)

Register allocation in hyper-block for EPIC processors. - Hansoo Kim 002; Kanchi Gopinath; Vinod Kathail (PARCO, 1999)

Fine Grained Register Allocation for EPIC Processors With Predication. - Hansoo Kim 002; Vinod Kathail; Kanchi Gopinath; Bhagirath Narahari (PDPTA, 1999)

Machine-Description Driven Compilers for EPIC and VLIW Processors. - B. Ramakrishna Rau; Vinod Kathail; Shail Aditya (Des. Autom. Embed. Syst., 1999)

High-Level Synthesis of Nonprogrammable Hardware Accelerators. - Robert Schreiber; Shail Aditya; B. Ramakrishna Rau; Vinod Kathail; Scott A. Mahlke; Santosh G. Abraham; Greg Snider (ASAP, 2000)

Compiling for EPIC architectures. - Vinod Kathail; Michael S. Schlansker; B. Ramakrishna Rau (Proc. IEEE, 2001)

PICO: Automatically Designing Custom Computers. - Vinod Kathail; Shail Aditya; Robert Schreiber; B. Ramakrishna Rau; Darren C. Cronquist; Mukund Sivaraman (Computer, 2002)

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. - Robert Schreiber; Shail Aditya; Scott A. Mahlke; Vinod Kathail; B. Ramakrishna Rau; Darren C. Cronquist; Mukund Sivaraman (J. VLSI Signal Process., 2002)

Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. - Vinod Kathail; Shail Aditya; Craig Gleason; Nagesh Chatekar (VLSI Design, 2007)

Architecture Exploration for Low Power Design. - Vinod Kathail; Tom Miller (VLSI Design, 2008)

Programming high performance signal processing systems in high level languages. - Kees A. Vissers; Devada Varma; Vinod Kathail; Jeff Bier; Don MacMillen; Joseph R. Cavallaro (FPGA, 2010)

UltraScale+ MPSoC and FPGA families. - Vamsi Boppana; Sagheer Ahmad; Ilya Ganusov; Vinod Kathail; Vidya Rajagopalan; Ralph Wittig (Hot Chips Symposium, 2015)

SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. - Vinod Kathail; James Hwang; Welson Sun; Yogesh Chobe; Tom Shui; Jorge Carrillo (FPGA, 2016)

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. - Sagheer Ahmad; Vamsi Boppana; Ilya Ganusov; Vinod Kathail; Vidya Rajagopalan; Ralph Wittig (IEEE Micro, 2016)

Xilinx Vitis Unified Software Platform. - Vinod Kathail (FPGA, 2020)

Parallelization Strategies for DLRM Embedding Bag Operator on AMD CPUs. - Krishnakumar Nair; Avinash-Chandra Pandey; Siddappa Karabannavar; Meena Arunachalam; John Kalamatianos; Varun Agrawal; Saurabh Gupta 002; Ashish Sirasao; Elliott Delaye; Steven K. Reinhardt; Rajesh Vivekanandham; Ralph Wittig; et al. (IEEE Micro, 2024)

AMD XDNA NPU in Ryzen AI Processors. - Alejandro Rico; Satyaprakash Pareek; Javier Cabezas; David Clarke; Baris Özgül; Francisco Barat; Yao Fu; Stephan Münz; Dylan Stuart; Patrick Schlangen; Pedro Duarte; Sneha Date; et al. (IEEE Micro, 2024)

Looking Back 25 Years to the HP Labs ASIC Synthesis Project, PICO. - Robert Schreiber; Shail Aditya; Vinod Kathail (ASAP, 2025)