A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design. - Mansi Jhamb; Vinod Kumar Khera; Piyush Pant; Hinduja Pudi (J. Circuits Syst. Comput., 2019)

A heuristic fault based optimization approach to reduce test vectors count in VLSI testing. - Vinod Kumar Khera; R. K. Sharma; A. K. Gupta (J. King Saud Univ. Comput. Inf. Sci., 2019)