A Disturb Decoupled Column Select 8T SRAM Cell. - Vinod Ramadurai; Rajiv V. Joshi; Rouwaida Kanj (CICC, 2007)

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. - Vinod Ramadurai; Harold Pilo; John Andersen; Geordie Braceras; John A. Gabric; Daniel Geise; Steve Lamphier; Yue Tan (IEEE J. Solid State Circuits, 2009)

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. - Rajiv V. Joshi; Rouwaida Kanj; Vinod Ramadurai (IEEE Trans. Very Large Scale Integr. Syst., 2011)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)