The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture. - Dana S. Henry; Bradley C. Kuszmaul; Vinod Viswanath (ARVLSI, 1999)

Multi-log Processor - Towards Scalable Event-Driven Multiprocessors. - Vinod Viswanath (DSD, 2004)

Automatic insertion of low power annotations in RTL for pipelined microprocessors. - Vinod Viswanath; Jacob A. Abraham; Warren A. Hunt Jr. (DATE, 2006)

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. - Shobha Vasudevan; Jacob A. Abraham; Vinod Viswanath; Jiajin Tu (MEMOCODE, 2006)

Efficient Microprocessor Verification using Antecedent Conditioned Slicing. - Shobha Vasudevan; Vinod Viswanath; Jacob A. Abraham (VLSI Design, 2007)

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. - Shobha Vasudevan; Vinod Viswanath; Robert W. Sumners; Jacob A. Abraham (IEEE Trans. Computers, 2007)

Sequential equivalence checking between system level and RTL descriptions. - Shobha Vasudevan; Vinod Viswanath; Jacob A. Abraham; Jiajin Tu (Des. Autom. Embed. Syst., 2008)

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. - Vinod Viswanath; Shobha Vasudevan; Jacob A. Abraham (VLSI Design, 2009)

Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. - Vinod Viswanath; Shobha Vasudevan; Jacob A. Abraham (J. Low Power Electron., 2009)

Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design. - Vinod Viswanath; Jacob A. Abraham (J. Low Power Electron., 2012)

Power Management Methods: From Specification and Modeling, to Techniques and Verification. - Vinod Viswanath; Rajeev Muralidhar; Harinarayanan Seshadri; Ananth S. Narayan (J. Low Power Electron., 2012)

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs. - Vinod Viswanath; Rajeev Muralidhar; Harinarayanan Seshadri; Jacob A. Abraham (ISQED, 2013)

Welcome. - Brian Cline; Saibal Mukhopadhyay; Peter J. Wright; Hai Li; Vinod Viswanath; Paul Wesling; Gang Qu 001; Ali Iranmanesh (ISQED, 2016)

Failures and verification solutions related to untimed paths in SOCs. - Pranav Ashar; Vikas Sachdeva; Vinod Viswanath (ISQED, 2017)

Closing the Verification Gap with Static Sign-off. - Pranav Ashar; Vinod Viswanath (ISQED, 2019)

DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications. - Vinod Viswanath; Kanad Chakraborty (VLSID, 2024)