Accuracy and speed limitations in DACs across CMOS process technologies. - Samantha M. Yoder; Sidharth Balasubramanian; Waleed Khalil; Vipul J. Patel (MWSCAS, 2013)

InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR. - Bert K. Oyama; Daniel Ching; Khanh Thai; Augusto Gutierrez-Aitken; Vipul J. Patel (IEEE J. Solid State Circuits, 2013)

A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis. - Jamin J. McCue; Brian Dupaix; Lucas Duncan; Brandon Mathieu; Samantha McDonnell; Vipul J. Patel; Tony Quach 001; Waleed Khalil (IEEE J. Solid State Circuits, 2016)

A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR. - Lucas Duncan; Brian Dupaix; Jamin J. McCue; Brandon Mathieu; Matthew LaRue; Vipul J. Patel; Mesfin Teshome; Myung-Jun Choe; Waleed Khalil (IEEE J. Solid State Circuits, 2017)

A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS. - Ramy Tantawy; Vipul J. Patel; Dale Shane Smith; Matthew J. Casto; Lucas Duncan; Brian Dupaix; Luciano Boglione; Joel Goodman; Waleed Khalil (ISCAS, 2018)

Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS. - Ramy Tantawy; Vipul J. Patel; Dale Shane Smith; S. M. Shahriar Rashid; Matthew J. Casto; Lucas Duncan; Roman Fragasse; Brian Dupaix; Luciano Boglione; Joel Goodman; Waleed Khalil (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)