Layout-Area Models for High-Level Synthesis. - Allen C.-H. Wu; Viraphol Chaiyakul; Daniel Gajski (ICCAD, 1991)

Timing models for high-level synthesis. - Viraphol Chaiyakul; Allen C.-H. Wu; Daniel D. Gajski (EURO-DAC, 1992)

Accurate layout area and delay modeling for system level design. - Champaka Ramachandran; Fadi J. Kurdahi; Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul (ICCAD, 1992)

High-Level Transformations for Minimizing Syntactic Variances. - Viraphol Chaiyakul; Daniel Gajski; Loganath Ramachandran (DAC, 1993)

An Algorithm for Array Variable Clustering. - Loganath Ramachandran; Daniel Gajski; Viraphol Chaiyakul (EDAC-ETC-EUROASIC, 1994)

Condition graphs for high-quality behavioral synthesis. - Hsiao-Ping Juan; Viraphol Chaiyakul; Daniel D. Gajski (ICCAD, 1994)

Clock-driven performance optimization in interactive behavioral synthesis. - Hsiao-Ping Juan; Daniel Gajski; Viraphol Chaiyakul (ICCAD, 1996)

Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. - Nong Fan; Viraphol Chaiyakul; Daniel Gajski (ASP-DAC, 2000)

Embedded tutorial: essential issues for IP reuse. - Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul; Shojiro Mori; Tom Nukiyama; Pierre Bricaud (ASP-DAC, 2000)