Software-Based Delay Fault Testing of Processor Cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (Asian Test Symposium, 2003)

Instruction-Based Delay Fault Self-Testing of Processor Cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (VLSI Design, 2004)

Testing Superscalar Processors in Functional Mode. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (FPL, 2005)

Instruction-based delay fault self-testing of pipelined processor cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (ISCAS (6), 2005)

Delay Fault Testing of Processor Cores in Functional Mode. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. - K. G. Deepak; Robinson Reyna; Virendra Singh; Adit D. Singh (Asian Test Symposium, 2009)

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (Asian Test Symposium, 2009)

Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. - Mikael Väyrynen; Virendra Singh; Erik Larsson (DATE, 2009)

On Minimization of Peak Power for Scan Circuit during Test. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Vishwani D. Agrawal (ETS, 2009)

DX-compactor: distributed X-compaction for SoCs. - Reshma C. Jumani; Niraj Bharatkumar Jain; Virendra Singh; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2009)

Polynomial coefficient based DC testing of non-linear analog circuits. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (ACM Great Lakes Symposium on VLSI, 2009)

Modified Scan Flip-Flop for Low Power Testing. - Amit Mishra 002; Nidhi Sinha; Satdev; Virendra Singh; Sreejit Chakravarty; Adit D. Singh (Asian Test Symposium, 2010)

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (DATE, 2010)

Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. - Dimitar Nikolov; Urban Ingelsson; Virendra Singh; Erik Larsson (DELTA, 2010)

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (DSN, 2010)

Modified T-Flip-Flop based scan cell for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Adit D. Singh (ETS, 2010)

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ETS, 2010)

On selection of state variables for delay test of identical functional units. - Aditi Kajala; Gayaprasad Sinsinwar; Rahul Raj Choudhary; Jaynarayan T. Tudu; Virendra Singh (EWDTS, 2010)

FREP: A soft error resilient pipelined RISC architecture. - Viney Kumar; Rahul Raj Choudhary; Virendra Singh (EWDTS, 2010)

Path delay faults and ENF. - Anzhela Yu. Matrosova; Valeriy B. Lipsky; Alexey Melnikov 002; Virendra Singh (EWDTS, 2010)

Thermal aware test scheduling for stacked multi-chip-modules. - N. S. Vinay; Indira Rawat; Erik Larsson; Manoj Singh Gaur; Virendra Singh (EWDTS, 2010)

Fault grading using Instruction-Execution graph. - K. R. Vinutha; Virendra Singh; Anzhela Yu. Matrosova; Manoj Singh Gaur (EWDTS, 2010)

SEU tolerant SRAM for FPGA applications. - Sudipta Sarkar; Anubhav Adak; Virendra Singh; Kewal K. Saluja; Masahiro Fujita (FPT, 2010)

Energy-efficient redundant execution for chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (ACM Great Lakes Symposium on VLSI, 2010)

Graph theoretic approach for scan cell reordering to minimize peak shift power. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ACM Great Lakes Symposium on VLSI, 2010)

Robust detection of soft errors using delayed capture methodology. - V. Prasanth 001; Virendra Singh; Rubin A. Parekhji (IOLTS, 2010)

Test application time minimization for RAS using basis optimization of column decoder. - A. Abhishek; Amanulla Khan; Virendra Singh; Kewal K. Saluja; Adit D. Singh (ISCAS, 2010)

Genetic algorithm based topology generation for application specific Network-on-Chip. - Naveen Choudhary; Manoj Singh Gaur; Vijay Laxmi; Virendra Singh (ISCAS, 2010)

On Minimization of Test Application Time for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Hideo Fujiwara; Adit D. Singh (VLSI Design, 2010)

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. - Suraj Sindia; Virendra Singh; Vishwani D. Agrawal (VLSI Design, 2010)

SSTKR: Secure and Testable Scan Design through Test Key Randomization. - Mohammed Abdul Razzaq; Virendra Singh; Adit D. Singh (Asian Test Symposium, 2011)

Test and Diagnosis of Analog Circuits Using Moment Generating Functions. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (Asian Test Symposium, 2011)

GA Based Congestion Aware Topology Generation for Application Specific NoC. - Naveen Choudhary; Manoj Singh Gaur; Vijay Laxmi; Virendra Singh (DELTA, 2011)

Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization. - Dimitar Nikolov; Urban Ingelsson; Virendra Singh; Erik Larsson (DSN Workshops, 2011)

Selection of the state variables for partial enhanced scan techniques. - Anzhela Yu. Matrosova; Alexey Melnikov 002; Ruslan Mukhamedov; Virendra Singh (EWDTS, 2011)

Parallelizing TUNAMI-N1 Using GPGPU. - Harsh Gidra; Israrul Haque; Nitin P. Kumar; M. Sargurunathan; Manoj Singh Gaur; Vijay Laxmi; Mark Zwolinski; Virendra Singh (HPCC, 2011)

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. - Pramod Subramanyan; Virendra Singh; Kewal K. Saluja; Erik Larsson (ICCD, 2011)

Reduced overhead soft error mitigation using error control coding techniques. - V. Prasanth 001; Virendra Singh; Rubin A. Parekhji (IOLTS, 2011)

SEU tolerant SRAM cell. - Sudipta Sarkar; Anubhav Adak; Virendra Singh; Kewal K. Saluja; Masahiro Fujita (ISQED, 2011)

Testing linear and non-linear analog circuits using moment generating functions. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (LATW, 2011)

Tutorial: "Post silicon debug of SOC designs". - Virendra Singh; Masahiro Fujita (SoCC, 2011)

C-Routing: An adaptive hierarchical NoC routing methodology. - Manas Kumar Puthal; Virendra Singh; Manoj Singh Gaur; Vijay Laxmi (VLSI-SoC, 2011)

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (VTS, 2011)

SEU tolerant robust memory cell design. - Mohammed Shayan; Virendra Singh; Adit D. Singh; Masahiro Fujita (IOLTS, 2012)

Impact of process variations on computers used for image processing. - Suraj Sindia; Fa Foster Dai; Vishwani D. Agrawal; Virendra Singh (ISCAS, 2012)

Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata. - Pawan Kumar; Virendra Singh (SIN, 2012)

SEU Tolerant Robust Latch Design. - Mohammed Shayan; Virendra Singh; Adit D. Singh; Masahiro Fujita (VDAT, 2012)

ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. - Jaynarayan T. Tudu; Deepak Malani; Virendra Singh (VDAT, 2012)

Derating based hardware optimizations in soft error tolerant designs. - V. Prasanth 001; Virendra Singh; Rubin A. Parekhji (VTS, 2012)

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (J. Electron. Test., 2012)

Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. - Suraj Sindia; Vishwani D. Agrawal; Virendra Singh (J. Electron. Test., 2012)

Thermal analysis and modeling of 3D integrated circuits for test scheduling. - Indira Rawat; M. K. Gupta; Virendra Singh (3DIC, 2013)

Delay testable sequential circuit designs. - Anzhela Yu. Matrosova; Eugeniy Mitrofanov; Virendra Singh (EWDTS, 2013)

PDF testability of the circuits derived by special covering ROBDDs with gates. - Anzhela Yu. Matrosova; Ekaterina Nikolaeva; Dmitry Kudin; Virendra Singh (EWDTS, 2013)

Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. - Anzhela Yu. Matrosova; Sergey Ostanin; Alexey Melnikov 002; Virendra Singh (EWDTS, 2013)

Scheduling tests for 3D SoCs with temperature constraints. - Indira Rawat; M. K. Gupta; Virendra Singh (EWDTS, 2013)

Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. - Jaynarayan T. Tudu; Deepak Malani; Virendra Singh (VDAT, 2013)

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. - Prabhat Mishra 001; Masahiro Fujita; Virendra Singh; Nagesh Tamarapalli; Sharad Kumar; Rajesh Mittal (VLSI Design, 2013)

Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. - Anzhela Yu. Matrosova; Sergey A. Ostanin; Virendra Singh (Autom. Remote. Control., 2013)

A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors. - Nahit Pawar; Madhu N. Belur; Mani Bhushan; A. P. Tiwari; M. G. Kelkar; M. Pramanik; Virendra Singh (EAIS, 2014)

Partially programmable circuit design. - Anzhela Yu. Matrosova; Sergey Ostanin; Irina Kirienko; Virendra Singh (EWDTS, 2014)

Temperature aware test scheduling by modified floorplanning. - Indira Rawat; M. K. Gupta; Virendra Singh (EWDTS, 2014)

Operand Isolation with Reduced Overhead for Low Power Datapath Design. - Lokesh Siddhu; Amit Mishra 002; Virendra Singh (VLSID, 2014)

Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems. - Dimitar Nikolov; Urban Ingelsson; Virendra Singh; Erik Larsson (Microelectron. Reliab., 2014)

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (ATS, 2015)

A Soft Error Resilient Low Leakage SRAM Cell Design. - Adithyalal P. M; Shankar Balachandran; Virendra Singh (ATS, 2015)

A Methodology for Identifying High Timing Variability Paths in Complex Designs. - Virendra Singh; Adit D. Singh; Kewal K. Saluja (ATS, 2015)

Application behavior aware re-reference interval prediction for shared LLC. - Parth Lathigara; Shankar Balachandran; Virendra Singh (ICCD, 2015)

PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. - Toral Shah; Anzhela Yu. Matrosova; Virendra Singh (VDAT, 2015)

Enabling LOS delay test with slow scan enable. - Satyadev Ahlawat; Darshit Vaghani; Rohini Gulve; Virendra Singh (EWDTS, 2016)

Performance modelling of heterogeneous ISA multicore architectures. - Nirmal Kumar Boran; Rameshwar Prasad Meghwal; Kuldeep Sharma; Binod Kumar 001; Virendra Singh (EWDTS, 2016)

ILP based don't care bits filling technique for reducing capture power. - Rohini Gulve; Virendra Singh (EWDTS, 2016)

A trace signal selection algorithm for improved post-silicon debug. - Binod Kumar 001; Ankit Jindal; Virendra Singh (EWDTS, 2016)

A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. - Binod Kumar 001; Boda Nehru; Brajesh Pandey; Virendra Singh; Jaynarayan T. Tudu (EWDTS, 2016)

ROBDD based path delay fault testable combinational circuit synthesis. - Toral Shah; Virendra Singh; Anzhela Yu. Matrosova (EWDTS, 2016)

A high performance scan flip-flop design for serial and mixed mode scan test. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (IOLTS, 2016)

REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. - Shoba Gopalakrishnan; Virendra Singh (IOLTS, 2016)

On Securing Scan Design from Scan-Based Side-Channel Attacks. - Satyadev Ahlawat; Darshit Vaghani; Jaynarayan T. Tudu; Virendra Singh (ATS, 2017)

Preventing scan-based side-channel attacks through key masking. - Satyadev Ahlawat; Darshit Vaghani; Virendra Singh (DFT, 2017)

REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture. - Shoba Gopalakrishnan; Virendra Singh (DFT, 2017)

An efficient test technique to prevent scan-based side-channel attacks. - Satyadev Ahlawat; Darshit Vaghani; Virendra Singh (ETS, 2017)

PHP: Power hungry pattern generation at higher abstraction level. - Rohini Gulve; Anshu Goel; Virendra Singh (EWDTS, 2017)

Achieving full functional coverage for the forwarding unit of pipelined processors. - V. S. Vineesh; Nihar Hage; B. Karthik; Virendra Singh (EWDTS, 2017)

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. - Binod Kumar 001; Ankit Jindal; Masahiro Fujita; Virendra Singh (ACM Great Lakes Symposium on VLSI, 2017)

EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads. - Abhishek Rajgadia; Newton; Virendra Singh (ACM Great Lakes Symposium on VLSI, 2017)

RTL level trace signal selection and coverage estimation during post-silicon validation. - Binod Kumar 001; Kanad Basu; Masahiro Fujita; Virendra Singh (HLDVT, 2017)

DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. - Newton; Sujit Kr Mahto; Suhit Pai; Virendra Singh (ICCD, 2017)

Revisiting random access scan for effective enhancement of post-silicon observability. - Binod Kumar 001; Ankit Jindal; Jaynarayan T. Tudu; Brajesh Pandey; Virendra Singh (IOLTS, 2017)

Instruction-based self-test for delay faults maximizing operating temperature. - Nihar Hage; Rohini Gulve; Masahiro Fujita; Virendra Singh (IOLTS, 2017)

Test pattern generation to detect multiple faults in ROBDD based combinational circuits. - Toral Shah; Anzhela Yu. Matrosova; Virendra Singh (IOLTS, 2017)

A low cost technique for scan chain diagnosis. - Satyadev Ahlawat; Darshit Vaghani; Rohini Gulve; Virendra Singh (ISCAS, 2017)

Exploiting path delay test generation to develop better TDF tests for small delay defects. - Ankush Srivastava; Adit D. Singh; Virendra Singh; Kewal K. Saluja (ITC, 2017)

Post-silicon observability enhancement with topology based trace signal selection. - Binod Kumar 001; Ankit Jindal; Masahiro Fujita; Virendra Singh (LATS, 2017)

Testing multiple stuck-at faults of ROBDD based combinational circuit design. - Toral Shah; Anzhela Yu. Matrosova; Binod Kumar 001; Masahiro Fujita; Virendra Singh (LATS, 2017)

Identifying high variability speed-limiting paths under aging. - Ankush Srivastava; Virendra Singh; Adit D. Singh; Kewal K. Saluja (LATS, 2017)

Improving post-silicon error detection with topological selection of trace signals. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Masahiro Fujita; Virendra Singh (VLSI-SoC, 2017)

On Testing of Superscalar Processors in Functional Mode for Delay Faults. - Nihar Hage; Rohini Gulve; Masahiro Fujita; Virendra Singh (VLSID, 2017)

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. - Binod Kumar 001; Ankit Jindal; Virendra Singh; Masahiro Fujita (VLSID, 2017)

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. - Ankush Srivastava; Virendra Singh; Adit D. Singh; Kewal K. Saluja (J. Electron. Test., 2017)

ATPG power guards: On limiting the test power below threshold. - Rohini Gulve; Virendra Singh (DATE, 2018)

Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. - Satyadev Ahlawat; Darshit Vaghani; Naveen Bazard; Virendra Singh (EWDTS, 2018)

AB-Aware: Application Behavior Aware Management of Shared Last Level Caches. - Suhit Pai; Newton Singh; Virendra Singh (ACM Great Lakes Symposium on VLSI, 2018)

A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. - Binod Kumar 001; Kanad Basu; Virendra Singh (IGSC, 2018)

A PAM-4 10S/12S line coding scheme with equi-probable levels. - Sandeep Goyal; Ron Joseph; Virendra Singh; Shalabh Gupta (ISCAS, 2018)

In-situ Monitoring for Slack Time Violation Without Performance Penalty. - Nihar Hage; Satyadev Ahlawat; Virendra Singh (ISCAS, 2018)

On Securing Scan Design Through Test Vector Encryption. - Darshit Vaghani; Satyadev Ahlawat; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (ISCAS, 2018)

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. - Ankit Jindal; Binod Kumar 001; Nitish Jindal; Masahiro Fujita; Virendra Singh (ISVLSI, 2018)

Memory-system requirements for convolutional neural networks. - Antara Ganguly; Virendra Singh; Rajeev Muralidhar; Masahiro Fujita (MEMSYS, 2018)

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. - Toral Shah; Anzhela Yu. Matrosova; Masahiro Fujita; Virendra Singh (J. Electron. Test., 2018)

Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. - Binod Kumar 001; Atul Kumar Bhosale; Masahiro Fujita; Virendra Singh (ATS, 2019)

Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. - Vineesh V. S.; Binod Kumar 001; Rushikesh Shinde; Akshay Jaiswal; Harsh Bhargava; Virendra Singh (ATS, 2019)

Preventing Scan Attack through Test Response Encryption. - Satyadev Ahlawat; Jaynarayan T. Tudu; Manoj Singh Gaur; Masahiro Fujita; Virendra Singh (DFT, 2019)

Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. - Raj Kumar Choudhary; Newton Singh; Harideep Nair; Rishabh Rawat; Virendra Singh (ICCD, 2019)

Securing Scan through Plain-text Restriction. - Satyadev Ahlawat; Kailash Ahirwar; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (IOLTS, 2019)

Towards Energy Efficient non-von Neumann Architectures for Deep Learning. - Antara Ganguly; Rajeev Muralidhar; Virendra Singh (ISQED, 2019)

A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. - Binod Kumar 001; Masahiro Fujita; Virendra Singh (VLSID, 2019)

On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. - Jaidev Shenoy; Kelly Ockunzzi; Virendra Singh; Kushal Kamal (VLSID, 2019)

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. - Binod Kumar 001; Masahiro Fujita; Virendra Singh (J. Electron. Test., 2019)

Soft-error reliable architecture for future microprocessors. - Shoba Gopalakrishnan; Virendra Singh (IET Comput. Digit. Tech., 2019)

LUT-based Circuit Approximation with Targeted Error Guarantees. - Vinod G. U; Vineesh V. S.; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (ATS, 2020)

Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. - Antara Ganguly; Shankar Balachandran; Anant V. Nori; Virendra Singh; Sreenivas Subramoney (ISPASS, 2020)

A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. - Binod Kumar 001; Swapniel Thakur; Kanad Basu; Masahiro Fujita; Virendra Singh (VLSID, 2020)

PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures. - Newton; Virendra Singh; Trevor E. Carlson (IEEE Comput. Archit. Lett., 2020)

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. - Binod Kumar 001; Kanad Basu; Masahiro Fujita; Virendra Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. - Binod Kumar 001; Jay Adhaduk; Kanad Basu; Masahiro Fujita; Virendra Singh (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Secrecy Rate Maximization at Near User in Untrusted NOMA with Trusted DF Relay. - Insha Amin; Deepak Mishra 001; Ravikant Saini; Virendra Singh (ANTS, 2021)

Predictive Warp Scheduling for Efficient Execution in GPGPU. - Abhinish Anand; Winnie Thomas; Suryakant Toraskar; Virendra Singh (ACM Great Lakes Symposium on VLSI, 2021)

Dynamic Optimizations in GPU Using Roofline Model. - Winnie Thomas; Suryakant Toraskar; Virendra Singh (ISCAS, 2021)

Enhancing Testbench Quality via Genetic Algorithm. - Harsh Bhargav; Vineesh V. S.; Binod Kumar 001; Virendra Singh (MWSCAS, 2021)

Fine-Grained Scheduling in Heterogeneous-ISA Architectures. - Nirmal Kumar Boran; Shubhankit Rathore; Meet Udeshi; Virendra Singh (IEEE Comput. Archit. Lett., 2021)

DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. - Arindam Sarkar; Newton Singh; Varun Venkitaraman; Virendra Singh (IEEE Comput. Archit. Lett., 2021)

Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter. - Vedant Satav; Virendra Singh (CoRR, 2021)

A Framework for Configurable Joint-Scan Design-for-Test Architecture. - Jaynarayan T. Tudu; Satyadev Ahlawat; Sonali Shukla; Virendra Singh (J. Electron. Test., 2021)

Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. - V. S. Vineesh; Binod Kumar 001; Rushikesh Shinde; Neelam Sharma; Masahiro Fujita; Virendra Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. - Raghunandana K. K; B. K. S. V. L. Varaprasad; Matteo Sonza Reorda; Virendra Singh (ISVLSI, 2022)

PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning. - Nirmal Kumar Boran; Pranil Joshi; Virendra Singh (SECRYPT, 2022)

Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. - Pooja Choudhary; Lava Bhargava; Masahiro Fujita; Virendra Singh (VDAT, 2022)

Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. - Ashwin Sanjay Lele; Srivatsava Jandhyala; Saurabh Gangurde; Virendra Singh; Sreenivas Subramoney; Udayan Ganguly (VDAT, 2022)

Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. - Anishetti Venkatesh; Chandan Kumar Jha 001; G. U. Vinod; Masahiro Fujita; Virendra Singh (VDAT, 2022)

Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. - Riccardo Cantoro; Francesco Garau; Riccardo Masante; Sandro Sartoni; Virendra Singh; Matteo Sonza Reorda (VTS, 2022)

Approximating Arithmetic Circuits for IoT Devices Data Processing. - Pooja Choudhary; Lava Bhargava; Masahiro Fujita; Virendra Singh; Ashok Kumar Suhag (Comput. Ind. Eng., 2022)

SMASh: A State Encoding Methodology Against Attacks on Finite State Machines. - Gowthami Konganapalle; Sonali Shukla; Virendra Singh (ATS, 2023)

On Attacking Scan-based Logic Locking Schemes. - Govind Rajhans Jadhav; Sonali Shukla; Virendra Singh (DFT, 2023)

DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (DFT, 2023)

Secure KNN Computation on Cloud. - Tikaram Sanyashi; Nirmal Kumar Boran; Virendra Singh (ICISS, 2023)

ERrOR: Improving Performance and Fault Tolerance Using Early Execution. - Raj Kumar Choudhary; Janeel Patel; Virendra Singh (IOLTS, 2023)

On-Chip SRAM Disclosure Attack Prevention Technique for SoC. - Prokash Ghosh; Yogesh Gholap; Virendra Singh (IOLTS, 2023)

TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. - Raghunandana K. K; B. K. S. V. L. Varaprasad; Matteo Sonza Reorda; Virendra Singh (IOLTS, 2023)

Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. - Pooja Choudhary; Lava Bhargava; G. U. Vinod; Ashok Kumar Suhag; Masahiro Fujita; Virendra Singh (iSES, 2023)

LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. - Pooja Choudhary; Lava Bhargava; Masahiro Fujita; Virendra Singh (LATS, 2023)

SSSN: Secured Streaming Scan Network. - Sonali Shukla; Bhavika Ranjeet Kumar; Virendra Singh (LATS, 2023)

TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. - Aditi Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh (SOSE, 2023)

TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (DDECS, 2024)

Physical-Design Aware Scan Cell Reordering for Low Power Testing. - Rohit Badjatya; N. S. Vinay; Rahul Kumar; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (EWDTS, 2024)

TRRR: Accelerated Online Error Detecting and Correcting Fault Tolerant Architecture. - Raghunandana K. K; Yogesh Prasad K. R; Matteo Sonza Reorda; Virendra Singh (EWDTS, 2024)

GNNDLD: Graph Neural Network with Directional Label Distribution. - Chandramani Chaudhary; Nirmal Kumar Boran; N. Sangeeth; Virendra Singh (ICAART (2), 2024)

MALAI: ML-Based Attack on Learning with Error Problem. - Mandru Suma Sri; Chakka Srikanth Yadav; Tikaram Sanyashi; Virendra Singh (ICISS, 2024)

SMS: Solving Many-sided RowHammer. - Samiksha Verma; Virendra Singh (MEMSYS, 2024)

S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks. - Tejeshwar Bhagatsing Thorawade; Prajakta Yeola; Varun Venkitaraman; Virendra Singh (SBAC-PAD, 2024)

Critical Behavior Sequence Monitoring for Early Malware Detection. - Tarun Bisht; Sarath Babu 003; Virendra Singh (SIN, 2024)

Early Execution for Soft Error Detection. - Raj Kumar Choudhary; Janeel Patel; Virendra Singh (VLSID, 2024)

MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. - Prakhar Diwan; Suryakant Toraskar; Varun Venkitaraman; Nirmal Kumar Boran; Chandramani Chaudhary; Virendra Singh (VLSID, 2024)

Security in 5G Network Slices: Concerns and Opportunities. - Virendra Singh; Mahendra Pratap Singh; Saumya Hegde; Maanak Gupta (IEEE Access, 2024)

BD-MDLC: Behavior description-based enhanced malware detection for windows environment using longformer classifier. - Sarath Babu 003; Virendra Singh (Comput. Secur., 2024)

Accelerating Neural Network Inference in Handwritten Digit Recognition - Comparative Study. - Winnie Thomas; Virendra Singh (Parallel Process. Lett., 2024)

DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. - Aditi Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh; Adnan M. Abu-Mahfouz (Pattern Recognit. Lett., 2024)

A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. - Aditi Gupta; Sukanya Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh (Clust. Comput., 2024)

A New Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits. - Anjum Riaz; Gaurav Kumar; Yamuna Prasad; Satyadev Ahlawat; Virendra Singh (ISCAS, 2025)

RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs. - Varun Venkitaraman; Shrasti Bhargava; Tejeshwar Bhagatsing Thorawade; K. Kokkiligadda; Rahul Kumar; Virendra Singh (ISCAS, 2025)

Stegoslayer: A Robust Browser-Integrated Approach for Thwarting Stegomalware. - Rushikesh Kawale; Sarath Babu 003; Virendra Singh (SECRYPT, 2025)

EDQKD: Enhanced-Dynamic Quantum Key Distributions with Improved Security and Key Rate. - Nikhil Kumar Parida; Sarath Babu 003; Neeraj Panwar; Virendra Singh (SECRYPT, 2025)

SCAM: Secure Shared Cache Partitioning Scheme to Enhance Throughput of CMPs. - Varun Venkitaraman; Rishab Ravi; Tejeshwar Bhagatsing Thorawade; Nirmal Kumar Boran; Virendra Singh (SECRYPT, 2025)

Lichen: Leveraging Coupled Heterogeneity. - Prakhar Diwan; Nirmal Kumar Boran; Virendra Singh (VLSID, 2025)

B-CAVE: A Robust Online Time Series Change Point Detection Algorithm Based on the Between-Class Average and Variance Evaluation Approach. - Aditi Gupta; Adeiza James Onumanyi; Satyadev Ahlawat; Yamuna Prasad; Virendra Singh (IEEE Trans. Knowl. Data Eng., 2025)