Automatic data path abstraction for verification of large scale designs. - Viresh Paruthi; Nazanin Mansouri; Ranga Vemuri (ICCD, 1998)

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. - Viresh Paruthi; Andreas Kuehlmann (ICCD, 2000)

Circuit-based Boolean Reasoning. - Andreas Kuehlmann; Malay K. Ganai; Viresh Paruthi (DAC, 2001)

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. - John M. Ludden; Wolfgang Roesner; Gerry M. Heiling; John R. Reysa; Jonathan R. Jackson; Bing-Lun Chu; Michael L. Behm; Jason Baumgartner; Richard D. Peterson; Jamee Abdulhafiz; William E. Bucy; John H. Klaus; et al. (IBM J. Res. Dev., 2002)

Robust Boolean reasoning for equivalence checking and functional property verification. - Andreas Kuehlmann; Viresh Paruthi; Florian Krohm; Malay K. Ganai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Scalable Automated Verification via Expert-System Guided Transformations. - Hari Mony; Jason Baumgartner; Viresh Paruthi; Robert Kanzelman; Andreas Kuehlmann (FMCAD, 2004)

Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. - Viresh Paruthi; Christian Jacobi 002; Kai Weber 001 (CHARME, 2005)

Exploiting suspected redundancy without proving it. - Hari Mony; Jason Baumgartner; Viresh Paruthi; Robert Kanzelman (DAC, 2005)

Automatic Formal Verification of Fused-Multiply-Add FPUs. - Christian Jacobi 002; Kai Weber 001; Viresh Paruthi; Jason Baumgartner (DATE, 2005)

Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . - Jason Baumgartner; Hari Mony; Viresh Paruthi; Robert Kanzelman; Geert Janssen (ICCD, 2006)

Formal verification of correctness and performance of random priority-based arbiters. - Krishnan Kailas; Viresh Paruthi; Brian Monwai (FMCAD, 2009)

Formal verification of arbiters using property strengthening and underapproximations. - Gadiel Auerbach; Fady Copty; Viresh Paruthi (FMCAD, 2010)

Large-scale application of formal verification: From fiction to fact. - Viresh Paruthi (FMCAD, 2010)

Hybrid verification of a hardware modular reduction engine. - Jun Sawada; Peter Sandon; Viresh Paruthi; Jason Baumgartner; Michael L. Case; Hari Mony (FMCAD, 2011)

Formal verification of error correcting circuits using computational algebraic geometry. - Alexey Lvov; Luis Alfonso Lastras-Montaño; Viresh Paruthi; Robert Shadowen; Ali El-Zein (FMCAD, 2012)

Automatic Verification of Floating Point Units. - Udo Krautz; Viresh Paruthi; Anand Arunagiri; Sujeet Kumar; Shweta Pujar; Tina Babinsky (DAC, 2014)

Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry. - Alexey Lvov; Luis Alfonso Lastras-Montaño; Barry M. Trager; Viresh Paruthi; Robert Shadowen; Ali El-Zein (Formal Methods Syst. Des., 2014)

Designer-level verification: an industrial experience story. - Stephen Bergman; Gabor Bobok; Walter Kowalski; Shlomit Koyfman; Shiri Moran; Ziv Nevo; Avigail Orni; Viresh Paruthi; Wolfgang Roesner; Gil Shurek; Vasantha Vuyyuru (DATE, 2015)

Solutions to IBM POWER8 verification challenges. - Klaus-Dieter Schubert; John M. Ludden; Salma Ayub; J. Behrend; Bishop Brock; Fady Copty; S. M. German; Oz Hershkovitz; H. Horbach; Jonathan R. Jackson; K. Keuerleber; J. Koesters; et al. (IBM J. Res. Dev., 2015)

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization. - Prashanth Vijayaraghavan; Apoorva Nitsure; Charles Mackin; Luyao Shi; Stefano Ambrogio; Arvind Haran; Viresh Paruthi; Ali El-Zein; Dan Coops; David Beymer; Tyler Baldwin; Ehsan Degan (MLCAD, 2024)