A Probabilistic Approach to Buffer Insertion. - Vishal Khandelwal; Azadeh Davoodi; Akash Nanavati; Ankur Srivastava 001 (ICCAD, 2003)

High level techniques for power-grid noise immunity. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (ACM Great Lakes Symposium on VLSI, 2004)

Variability inspired implementation selection problem. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (ICCAD, 2004)

Efficient statistical timing analysis through error budgeting. - Vishal Khandelwal; Azadeh Davoodi; Ankur Srivastava 001 (ICCAD, 2004)

Wire-length prediction using statistical techniques. - Jennifer L. Wong; Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001; Miodrag Potkonjak (ICCAD, 2004)

Empirical models for net-length probability distribution and applications. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A general framework for accurate statistical timing analysis considering correlations. - Vishal Khandelwal; Ankur Srivastava 001 (DAC, 2005)

Simultaneous Vt selection and assignment for leakage optimization. - Vishal Khandelwal; Azadeh Davoodi; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Probabilistic Evaluation of Solutions in Variability-Driven Optimization. - Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A statistical methodology for wire-length prediction. - Jennifer L. Wong; Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001; Miodrag Potkonjak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Monte-Carlo driven stochastic optimization framework for handling fabrication variability. - Vishal Khandelwal; Ankur Srivastava 001 (ICCAD, 2007)

Statistical timing analysis using Kernel smoothing. - Jennifer L. Wong; Azadeh Davoodi; Vishal Khandelwal; Ankur Srivastava 001; Miodrag Potkonjak (ICCD, 2007)

Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. - Vishal Khandelwal; Ankur Srivastava 001 (ISPD, 2007)

Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. - Ashish Dobhal; Vishal Khandelwal; Azadeh Davoodi; Ankur Srivastava 001 (VLSI Design, 2007)

Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. - Ashish Dobhal; Vishal Khandelwal; Ankur Srivastava 001 (VLSI Design, 2007)

Active mode leakage reduction using fine-grained forward body biasing strategy. - Vishal Khandelwal; Ankur Srivastava 001 (Integr., 2007)

Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. - Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. - Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Variability-Aware VLSI Design Automation For Nanoscale Technologies. - Vishal Khandelwal (2007)

Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. - Vishal Khandelwal; Ankur Srivastava 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Basic Algorithmic Techniques. - Vishal Khandelwal; Ankur Srivastava 001 (Handbook of Algorithms for Physical Design Automation, 2008)

On improving optimization effectiveness in interconnect-driven physical synthesis. - Prashant Saxena; Vishal Khandelwal; Changge Qiao; Pei-Hsin Ho; J.-C. Lin; Mahesh A. Iyer (ISPD, 2009)

Machine-Learning Enabled Next-Generation Physical Design - An EDA Perspective. - Vishal Khandelwal (MLCAD, 2020)

RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. - Yi-Chen Lu; Siddhartha Nath; Vishal Khandelwal; Sung Kyu Lim (DAC, 2021)

Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. - Yi-Chen Lu; Siddhartha Nath; Vishal Khandelwal; Sung Kyu Lim (ICCAD, 2021)

Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes. - Siddhartha Nath; Vishal Khandelwal (ISPD, 2021)

Machine-Learning Enabled PPA Closure for Next-Generation Designs. - Vishal Khandelwal (ISPD, 2022)

Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction. - Yi-Chen Lu; Wei-Ting Chan; Vishal Khandelwal; Sung Kyu Lim (MLCAD, 2022)

RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning. - Yi-Chen Lu; Wei-Ting Chan; Deyuan Guo; Sudipto Kundu; Vishal Khandelwal; Sung Kyu Lim (DAC, 2023)