A New Gate for Optimal Fault Tolerant & Testable Reversible Sequential Circuit Design. - Vishal Pareek (CoRR, 2014)

Secure and efficient fully dynamic group signature based on RSIS and RLWE. - Vishal Pareek; Chinmoy Biswas; Aditi Kar Gangopadhyay; Sugata Gangopadhyay (Peer Peer Netw. Appl., 2025)