A Non-invasive, Multi-modality Approach Based on NIRS and MRI Techniques For Monitoring Intracranial Brain Tumor Angiogenesis. - Vishal Saxena; Jon-Fredrik Nielsen; Ignacio Gonzalez-Gomez; Gevorg Karapetyan; Vazgen Khankaldyyan; Marvin D. Nelson Jr.; Walter E. Laug (AIPR, 2005)

Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs. - Rajaram Mohan Roy Koppula; Sakkarapani Balagopal; Vishal Saxena (SoCC, 2011)

Design of wideband continuous-time ΔΣ ADCs using two-step quantizers. - Sakkarapani Balagopal; Vishal Saxena (MWSCAS, 2012)

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-ΔΣ ADC with 1.5 cycle quantizer delay and improved STF. - Sakkarapani Balagopal; Vishal Saxena (MWSCAS, 2012)

Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion. - Sakkarapani Balagopal; Kehan Zhu; Vishal Saxena (MWSCAS, 2013)

Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects. - Kehan Zhu; Sakkarapani Balagopal; Vishal Saxena; Wan Kuang (MWSCAS, 2013)

Compact Verilog-A modeling of silicon traveling-wave modulator for hybrid CMOS photonic circuit design. - Kehan Zhu; Vishal Saxena; Wan Kuang (MWSCAS, 2014)

A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing. - Xinyu Wu 002; Vishal Saxena; Kehan Zhu (IJCNN, 2015)

A comprehensive design approach for a MZM based PAM-4 silicon photonic transmitter. - Kehan Zhu; Vishal Saxena; Xinyu Wu 002 (MWSCAS, 2015)

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition. - Xinyu Wu 002; Vishal Saxena; Kehan Zhu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning. - Xinyu Wu 002; Vishal Saxena; Kehan Zhu; Sakkarapani Balagopal (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Design Considerations for Traveling-Wave Modulator-Based CMOS Photonic Transmitters. - Kehan Zhu; Vishal Saxena; Xinyu Wu 002; Wan Kuang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Tutorial 4B: ADC design - from system architecture to transistor level design. - Bhibhudatta Sahoo; Vishal Saxena; Karan S. Bhatia (SoCC, 2016)

Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitter. - Kehan Zhu; Vishal Saxena; Xinyu Wu 002 (SoCC, 2016)

Enabling bio-plausible multi-level STDP using CMOS neurons with dendrites and bistable RRAMs. - Xinyu Wu 002; Vishal Saxena (IJCNN, 2017)

Realization of a 10 GHz PLL in IBM 130 nm SiGe BiCMOS process for optical transmitter. - Kehan Zhu; Sakkarapani Balagopal; Xinyu Wu 002; Vishal Saxena (ISCAS, 2017)

Behavioral modeling and characterization of silicon photonic Mach-Zehnder modulator. - Kehan Zhu; Rui Wang; Xinyu Wu 002; Vishal Saxena (MWSCAS, 2017)

Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices. - Vishal Saxena; Xinyu Wu 002; Ira Srivastava; Kehan Zhu (NANOCOM, 2017)

Case Study of a Hybrid Optoelectronic Limiting Receiver. - Kehan Zhu; Vishal Saxena (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. - Cheng Li; Kunzhi Yu; Jinsoo Rhim; Kehan Zhu; Nan Qi; Marco Fiorentino; Thierry Pinguet; Mark Peterson; Vishal Saxena; Samuel Palermo (BCICTS, 2018)

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip. - Vishal Saxena; Xinyu Wu 002; Kehan Zhu (ISCAS, 2018)

A Compact CMOS Memristor Emulator Circuit and its Applications. - Vishal Saxena (MWSCAS, 2018)

Design and Modeling of Silicon Photonic Ring-Based Linearized RF-to-Optical Modulator. - Md Jubayer Shawon; Rui Wang; Vishal Saxena (MWSCAS, 2018)

Design and Compact Modeling of Silicon-Photonic Coupling-Based Ring Modulators for Optical Interconnects. - Rui Wang; Md Jubayer Shawon; Vishal Saxena (MWSCAS, 2018)

Dendritic-Inspired Processing Enables Bio-Plausible STDP in Compound Binary Synapses. - Xinyu Wu 002; Vishal Saxena (CoRR, 2018)

From Design to Test: A High-Speed PRBS. - Kehan Zhu; Vishal Saxena (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Feature Extraction using Spiking Convolutional Neural Networks. - Ruthvik Vaila; John N. Chiasson; Vishal Saxena (ICONS, 2019)

High LRS-Resistance CMOS Memristive Synapses for Energy-Efficient Neuromorphic SoCs. - Vishal Saxena (MWSCAS, 2019)

A CMOS Photonic Optical PAM4 Transmitter Linearized using Three-Segment Ring Modulator. - Rui Wang; Vishal Saxena (MWSCAS, 2019)

Deep Convolutional Spiking Neural Networks for Image Classification. - Ruthvik Vaila; John N. Chiasson; Vishal Saxena (CoRR, 2019)

Continuous Learning in a Single-Incremental-Task Scenario with Spike Features. - Ruthvik Vaila; John N. Chiasson; Vishal Saxena (ICONS, 2020)

A Process-Variation Robust RRAM-Compatible CMOS Neuron for Neuromorphic System-on-a-Chip. - Vishal Saxena (ISCAS, 2020)

Analysis of RF Photonic Link using Silicon Photonic Ring-Assisted Mach Zehnder Modulator. - Md Jubayer Shawon; Vishal Saxena (MWSCAS, 2020)

Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models. - Md Jubayer Shawon; Vishal Saxena (IEEE Trans. Circuits Syst., 2020)

A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits. - Vishal Saxena (ISCAS, 2021)

Analysis of Trade-offs in RF Photonic Links based on Multi-Bias Tuning of Silicon Photonic Ring-Assisted Mach Zehnder Modulators. - Md Jubayer Shawon; Vishal Saxena (CoRR, 2021)

Mixed-Signal Neuromorphic Computing Circuits Using Hybrid CMOS-RRAM Integration. - Vishal Saxena (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Hybrid CMOS-RRAM Spiking CNNs with Time-Domain Max-pooling and Integrator Re-use. - Anuar Dorzhigulov; Shubham Mishra; Vishal Saxena (ISCAS, 2022)

A Hybrid CMOS Photonic 25Gbps Microring Transmitter with a -0.5-1.2V Direct-Coupled Drive. - Shubham Mishra; Md Jubayer Shawon; Anuar Dorzhigulov; Vishal Saxena (ISCAS, 2022)

A Deep Unsupervised Feature Learning Spiking Neural Network With Binarized Classification Layers for the EMNIST Classification. - Ruthvik Vaila; John N. Chiasson; Vishal Saxena (IEEE Trans. Emerg. Top. Comput. Intell., 2022)

Power Linear DACs (PLDACs) for Configuration and Control of Silicon Photonic Integrated Circuits. - Vikas Kumar; Shubham Mishra; Vishal Saxena (ISCAS, 2023)

A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh. - Md Jubayer Shawon; Vishal Saxena (ISSCC, 2023)

Automatic In-situ Optical Linearization of Silicon Photonic Ring-Assisted MZ Modulator for Integrated RF Photonic SoCs. - Md Jubayer Shawon; Vishal Saxena (OFC, 2023)

Compact Modeling and Rapid Simulation of Silicon Photonic Micro-Disk and Ring Modulators. - Vishal Saxena; Md Jubayer Shawon (CoRR, 2023)

A Sub-1pJ/bit Laser Power Independent 32Gb/s Silicon Photonic EAM Driver in 65nm CMOS. - Shubham Mishra; Vishal Saxena (ISCAS, 2024)

Compact Convolutional SNN Architecture for the Neuromorphic Speech Denoising. - Anuar Dorzhigulov; Vishal Saxena (MWSCAS, 2024)

A 7×4 Silicon Photonic Reconfigurable Optical Analog Processor with Algorithmic Calibration. - Md Jubayer Shawon; Vishal Saxena (OFC, 2024)

Optical Interconnects Using Hybrid Integration of CMOS and Silicon-Photonic ICs. - Vishal Saxena; Ankur Kumar; Shubham Mishra; Samuel Palermo; Kadaba R. Lakshmikumar (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Electronic Photonic Integrated Circuits (EPICs): Fundamentals and Applications. - Vishal Saxena (ISCAS, 2025)