A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. - Vishal Sharma 004; Pranshu Bisht; Abhishek Dalal; Shailesh Singh Chouhan; H. S. Jattana; Santosh Kumar Vishvakarma (VDAT, 2018)

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes. - Vishal Sharma 004; Santosh Kumar Vishvakarma; Shailesh Singh Chouhan; Kari Halonen (Int. J. Circuit Theory Appl., 2018)

ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology. - Lu Lu 013; Ju Eon Kim; Vishal Sharma 004; Tony Tae-Hyoung Kim (APCCAS, 2020)

A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. - Gopal Raut; Ambika Prasad Shah; Vishal Sharma 004; Gunjan Rajput; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2020)

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing. - Vishal Sharma 004; Ju Eon Kim; Yong-Jun Jo; Yuzong Chen 001; Tony Tae-Hyoung Kim (ISCAS, 2021)

A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices. - Vishal Sharma 004; Ju Eon Kim; Hyunjoon Kim; Lu Lu 013; Tony Tae-Hyoung Kim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications. - Vishal Sharma 004; Hyunjoon Kim; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs. - Xin Zhang 025; Vishal Sharma 004; Yuncheng Lu; Yong-Jun Jo; Tony Tae-Hyoung Kim (A-SSCC, 2023)

Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. - Gopal Raut; Jogesh Mukala; Vishal Sharma 004; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2023)

In-Memory Computing with 6T SRAM for Multi-operator Logic Design. - Narendra Singh Dhakad; Eshika Chittora; Gopal Raut; Vishal Sharma 004; Santosh Kumar Vishvakarma (Circuits Syst. Signal Process., 2024)

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation. - Junjie Mu; Lu Lu 013; Ju Eon Kim; Byung-Kwon An; Vishal Sharma 004; Arya Jagath Lekshmi; Putu Andhita Dananjaya; Weng Hong Lai; Wen Siang Lew; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)